DP8420V Datasheet, PDF (15/60 Pages) National Semiconductor (TI) – microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

4 0 Port A Access Modes (Continued)
4 3 EXTENDING CAS WITH EITHER ACCESS MODE
In both access modes once AREQ is negated RAS and
DTACK if programmed will be negated If ECAS0 was as-
serted (0) during programming CAS (CASs) will be negated
with AREQ If ECAS0 was negated (1) during programming
CAS (CASs) will continue to be asserted after RAS has
been negated given that the appropriate ECAS inputs are
asserted This allows a DRAM to have data present on the
data out bus while gaining RAS precharge time
FIGURE 9a Access Mode 0 Extending CAS
TL F 11109 – 11
FIGURE 9b Access Mode 1 Extending CAS
TL F 11109 – 12
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