LMH6554_14 Datasheet, PDF (14/24 Pages) National Semiconductor (TI) – LMH6554 2.8 GHz Ultra Linear Fully Differential Amplifier

LMH6554
SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013
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Split Supply Operation
For optimum performance, split supply operation is recommended using +2.5V and −2.5V supplies; however,
operation is possible on split supplies as low as +2.35V and −2.35V and as high as +2.65V and −2.65V.
Provided the total supply voltage does not exceed the 4.7V to 5.3V operating specification, non-symmetric supply
operation is also possible and in some cases advantageous. For example, if a 5V DC coupled operation is
required for low power dissipation but the amplifier input common mode range prevents this operation, it is still
possible with split supplies of (V+) and (V-). Where (V+)-(V-) = 5V and V+ and V- are selected to center the
amplifier input common mode range to suit the application.
Driving Analog To Digital Converters
Analog-to-digital converters present challenging load conditions. They typically have high impedance inputs with
large and often variable capacitive components. Figure 34 shows the LMH6554 driving an ultra-high-speed
Gigasample ADC the ADC10D1500. The LMH6554 common mode voltage is set by the ADC10D1500. The
circuit in Figure 34 has a 2nd order bandpass LC filter across the differential inputs of the ADC10D1500. The
ADC10D1500 is a dual channel 10–bit ADC with maximum sampling rate of 3 GSPS when operating in a single
channel mode and 1.5 GSPS in dual channel mode.
Figure 33 shows the SFDR and SNR performance vs. frequency for the LMH6554 and ADC10D1500
combination circuit with the ADC input signal level at −1dBFS. In order to properly match the input impedance
seen at the LMH6554 amplifier inputs, R_M is chosen to match Z_S || R_T for proper input balance. The amplifier is
configured to provide a gain of 2 V/V in single to differential mode. An external bandpass filter is inserted in
series between the input signal source and the amplifier to reduce harmonics and noise from the signal
generator.
90
85
80
75
SFDR (dBm)
70
65
60
55
50
SNR (dBFs)
45
40
0 100 200 300 400 500 600 700 750
INPUT FREQUENCY (MHz)
Figure 33. LMH6554 / ADC10D1500 SFDR and SNR Performance vs. Frequency
The amplifier and ADC should be located as close together as possible. Both devices require that the filter
components be in close proximity to them. The amplifier needs to have minimal parasitic loading on it's outputs
and the ADC is sensitive to high frequency noise that may couple in on its inputs. Some high performance ADCs
have an input stage that has a bandwidth of several times its sample rate. The sampling process results in all
input signals presented to the input stage mixing down into the first Nyquist zone (DC to Fs/2).
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