LM4856 Datasheet, PDF (14/23 Pages) National Semiconductor (TI) – Integrated Audio Amplifier System

Application Information
I²C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ADR: This is the address select input pin.
I²C INTERFACE
The LM4856 uses a serial bus, which conforms to the I²C
protocol, to control the chip’s functions with two wires: clock
and data. The clock line is uni-directional. The data line is
bi-directional (open-collector) with a pullup resistor (typically
10kΩ).The maximum clock frequency specified by the I²C
standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4856.
The I²C address for the LM4856 is determined using the
ADR pin. The LM4856’s two possible I²C chip addresses are
of the form 110110X₁0 (binary), where the X₁ = 0, if ADR is
logic low; and X₁ = 1, if ADR is logic high. If the I²C interface
is used to address a number of chips in a system and the
LM4856’s chip address can be changed to avoid address
conflicts.
The timing diagram for the I²C is shown in Figure 2. The data
is latched in on the stable high level of the clock and the data
line should be held high when not in use. The timing diagram
is broken up into six major sections:
The “start” signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I²C bus to check the incoming ad-
dress against their own chip address.
The 8-bit chip address is sent next, most significant bit first.
Each address bit must be stable while the clock level is high.
After the last bit of the address is sent, the master checks for
the LM4856’s acknowledge. The master releases the data
line high (through a pullup resistor). Then the master sends
a clock pulse. If the LM4856 has received the address
correctly, then it holds the data line low during the clock
pulse. If the data line is not low, then the master should send
a “stop” signal (discussed later) and abort the transfer.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
After the data byte is sent, the master must generate another
acknowledge to see if the LM4856 received the data.
If the master has more data bytes to send to the LM4856,
then the master can repeat the previous two steps until all
data bytes have been sent.
The “stop” signal ends the transfer. To signal “stop”, the data
signal goes high while the clock signal is high.
FIGURE 2. I²C Bus Format
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FIGURE 3. I²C Timing Diagram
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