LM4549 Datasheet, PDF (14/18 Pages) National Semiconductor (TI) – AC ’97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound

Application Information (Continued)
DS101035-7
FIGURE 7. Start of Audio Input Frame
Bit
Description
Comment
15
Codec Ready
Bit
0=Not Ready, 1=Ready
14
Slot 1 data
valid
Status Address is valid
13
Slot 2 data
valid
Status Data is valid
12
Slot 3 data
valid
Left Audio PCM Data is
valid
11
Slot 4 data
valid
Right Audio PCM Data is
valid
SDATA_IN Slot 1: Status Address / Slot Request Bits
This slot echoes the control register which a read was re-
quested on. The address echoed was initiated by a read re-
quest in the previous SDATA_OUT frame, slot 1. Bits 11 and
10 are slot request bits that support Sample Rate Conver-
sion (SRC) functionality. If bit 11 is set to 0, then the control-
ler should respond with a valid PCM left sample in slot 3 of
the next frame. If bit 10 is set to 0, then the controller should
respond with a valid PCM right sample in slot 4 of the next
frame. If bits 11 or 10 are set to 1, the controller should not
send data in the next frame. Bits 9 through 2 are unused.
Bits 1 and 0 are reserved and should be set to 0.
Bits
19
18:12
11
10
Description
Reserved
Control
Register Index
Slot 3
Request bit
(PCM left)
Slot 4
Request bit
(PCM right)
Comment
Stuffed with ″0″
Echo of Control Register
for which data is being
returned.
0 = Controller should
send valid slot 3 data in
the next frame, 1 =
Controller should not
send slot 3 data in the
next frame
0 = Controller should
send valid slot 4 data in
the next frame, 1 =
Controller should not
send slot 4 data in the
next frame
Bits
Description
Comment
9:2
Other Slot
Request bits
Unused - stuff with ″0″
1,0
Reserved
Stuff with ″0″
SDATA_IN Slot 2: Status Data
The slot returns the control register data. The data returned
was initiated by a read request in the previous SDATA_OUT
frame, slot 1.
Bits
Description
Control
19:4 Register Read
Data
3:0
Reserved
Comment
Stuffed with ″0″ ’s
SDATA_IN Slot 3: PCM Record Left Channel
This slot contains the left ADC sample data. The signal to be
digitized is selected via register 1Ah and subsequently
routed through the Input Mux for recording by the left ADC.
This is a 20-bit slot, where the digitized 18-bit PCM data is
output from the codec MSB first and the last remaining 2 bits
will zeros.
Bits
Description
Comment
19:2
PCM Record
Left Channel
18 bit audio sample from
left ADC
data
1:0
Reserved
Stuffed with ″0″’s
SDATA_IN Slot 4: PCM Record Right Channel
This slot contains the right ADC sample data. The signal digi-
tized is selected via register 1Ah and subsequently routed
through the Input Mux for recording by the right ADC. This is
a 20-bit slot, where the digitized 18-bit PCM data is output
from the codec MSB first and the last remaining 2 bits will ze-
ros.
Bits
Description
Comment
19:2
PCM Record
Right Channel
18 bit audio sample from
data
right ADC
1:0
Reserved
Stuffed with ″0″’s
SDATA_IN Slots 5-12: Reserved
These SDATA_IN slots are set to ″0″ as they are reserved for
future use.
AC Link Low Power Mode
DS101035-9
FIGURE 8. AC Link Powerdown Timing
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