LMK03002 Datasheet, PDF (13/24 Pages) National Semiconductor (TI) – Precision Clock Conditioner with Integrated VCO

2.3 REGISTERS R0, R4 to R7
Registers R4 through R7 control the four clock outputs. Reg-
ister R3 controls CLKout0, Register R4 controls CLKout1, and
so on. There is one additional bit in register R0 called RESET.
The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and
CLKoutX_EN denote the actual clock output which may be
from 0 to 3.
2.3.1 RESET bit -- R0 only
This bit is only in register R0. The use of this bit is optional
and it should be set to '0' if not used. Setting this bit to a '1'
Bit Name
RESET
CLKoutX_MUX
CLKoutX_EN
CLKoutX_DIV
CLKoutX_DLY
DIV4
OSCin_FREQ
VCO_R4_LF
VCO_R3_LF
VCO_C3_C4_LF
EN_Fout
EN_CLKout_Global
POWERDOWN
PLL_MUX
PLL_R
PLL_CP_GAIN
VCO_DIV
PLL_N
Default
Bit Value
Bit State
0 No reset, normal operation
0 Bypassed
0 Disabled
1 Divide by 2
0 0 ps
0 _{PDF ≤ 20 MHz}
10 10 MHz OSCin
0 Low (~200 Ω)
0 Low (~600 Ω)
0 C3 = 0 pF, C4 = 10 pF
0 Fout disabled
1 Normal - CLKouts normal
0 Normal - Device active
0 Disabled
10 R divider = 10
0 100 uA
2 Divide by 2
760 N divider = 760
2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each clock
output. Changing between the different modes changes the
blocks in the signal path and therefore incurs a delay relative
to the bypass mode. The different MUX modes and associ-
ated delays are listed below.
CLKoutX_MUX
[1:0]
Mode
Added Delay
Relative to
Bypass Mode
0
Bypassed (default)
0 ps
1
Divided
100 ps
400 ps
2
Delayed
(In addition to the
programmed
delay)
500 ps
3
Divided and (In addition to the
Delayed
programmed
delay)
2.3.3 CLKoutX_DIV[7:0] -- Clock Output Dividers
These bits control the clock output divider value. In order for
these dividers to be active, the respective CLKoutX_MUX
(See 2.3.2) bit must be set to either "Divided" or "Divided and
Delayed" mode. After all the dividers are programed, the
forces all registers to their power on reset condition and there-
fore automatically clears this bit. If this bit is set, all other R0
bits are ignored and R0 needs to be programmed again if
used with its proper values and RESET = 0.
Bit Description
Register
Bit
Location
Reset to power on defaults
R0
31
CLKoutX mux mode
18:17
CLKoutX enable
CLKoutX clock divide
16
R0 to R7
15:8
CLKoutX clock delay
7:4
Phase Detector Frequency
R11
15
OSCin Frequency in MHz
21:14
R4 internal loop filter values
R3 internal loop filter values
13:11
R13
10:8
C3 and C4 internal loop filter values
7:4
Fout enable
28
Global clock output enable
27
Device power down
R14
26
Multiplexer control for LD pin
23:20
PLL R divide value
19:8
Charge pump current
31:30
VCO divide value
R15
29:26
PLL N divide value
25:8
SYNC* pin must be used to ensure that all edges of the clock
outputs are aligned (See 1.7). The Clock Output Dividers fol-
low the VCO Divider so the final clock divide for an output is
VCO Divider × Clock Output Divider. By adding the divider
block to the output path a fixed delay of approximately 100 ps
is incurred.
The actual Clock Output Divide value is twice the binary value
programmed as listed in the table below.
CLKoutX_DIV[7:0]
Clock Output
Divider value
00000000
Invalid
0 0 0 0 0 0 0 1 2 (default)
00000010
4
00000011
6
00000100
8
00000101
10
........
...
11111111
510
2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays
These bits control the delay stages for each clock output. In
order for these delays to be active, the respective
CLKoutX_MUX (See 2.3.2) bit must be set to either "Delayed"
or "Divided and Delayed" mode. By adding the delay block to
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