LP3856-ADJ Datasheet, PDF (12/15 Pages) National Semiconductor (TI) – 3A Fast Response Ultra Low Dropout Linear Regulators

Application Hints (Continued)
PCB layout is also critical in high noise environments, since
RFI/EMI is easily radiated directly into PC traces. Noisy
circuitry should be isolated from "clean" circuits where pos-
sible, and grounded through a separate path. At MHz fre-
quencies, ground planes begin to look inductive and RFI/
EMI can cause ground bounce across the ground plane.
In multi-layer PCB applications, care should be taken in
layout so that noisy power and ground planes do not radiate
directly into adjacent layers which carry analog power and
ground.
OUTPUT NOISE
Noise is specified in two ways-
Spot Noise or Output noise density is the RMS sum of all
noise sources, measured at the regulator output, at a spe-
cific frequency (measured with a 1Hz bandwidth). This type
of noise is usually plotted on a curve as a function of fre-
quency.
Total output Noise or Broad-band noise is the RMS sum
of spot noise over a specified bandwidth, usually several
decades of frequencies.
Attention should be paid to the units of measurement. Spot
noise is measured in units µV/√Hz or nV/√Hz and total output
noise is measured in µV(rms).
The primary source of noise in low-dropout regulators is the
internal reference. In CMOS regulators, noise has a low
frequency component and a high frequency component,
which depend strongly on the silicon area and quiescent
current. Noise can be reduced in two ways: by increasing the
transistor area or by increasing the current drawn by the
internal reference. Increasing the area will decrease the
chance of fitting the die into a smaller package. Increasing
the current drawn by the internal reference increases the
total supply current (ground pin current). Using an optimized
trade-off of ground pin current and die size, LP3856-ADJ
achieves low noise performance and low quiescent current
operation.
The total output noise specification for LP3856-ADJ is pre-
sented in the Electrical Characteristics table. The Output
noise density at different frequencies is represented by a
curve under typical performance characteristics.
SHORT-CIRCUIT PROTECTION
The LP3856-ADJ is short circuit protected and in the event of
a peak over-current condition, the short-circuit control loop
will rapidly drive the output PMOS pass element off. Once
the power pass element shuts down, the control loop will
rapidly cycle the output on and off until the average power
dissipation causes the thermal shutdown circuit to respond
to servo the on/off cycling to a lower frequency. Please refer
to the section on thermal information for power dissipation
calculations.
SHUTDOWN OPERATION
A CMOS Logic level signal at the shutdown ( SD) pin will
turn-off the regulator. Pin SD must be actively terminated
through a 10kΩ pull-up resistor for a proper operation. If this
pin is driven from a source that actively pulls high and low
(such as a CMOS rail to rail comparator), the pull-up resistor
is not required. This pin must be tied to Vin if not used.
DROPOUT VOLTAGE
The dropout voltage of a regulator is defined as the minimum
input-to-output differential required to stay within 2% of the
nominal output voltage. For CMOS LDOs, the dropout volt-
age is the product of the load current and the Rds(on) of the
internal MOSFET.
REVERSE CURRENT PATH
The internal MOSFET in LP3856-ADJ has an inherent para-
sitic diode. During normal operation, the input voltage is
higher than the output voltage and the parasitic diode is
reverse biased. However, if the output is pulled above the
input in an application, then current flows from the output to
the input as the parasitic diode gets forward biased. The
output can be pulled above the input as long as the current
in the parasitic diode is limited to 200mA continuous and 1A
peak.
POWER DISSIPATION/HEATSINKING
The LP3856-ADJ can deliver a continuous current of 3A over
the full operating temperature range. A heatsink may be
required depending on the maximum power dissipation and
maximum ambient temperature of the application. Under all
possible conditions, the junction temperature must be within
the range specified under operating conditions. The total
power dissipation of the device is given by:
P_D = (V_IN−V_OUT)I_OUT+ (V_IN)I_GND
where I_GND is the operating ground current of the device
(specified under Electrical Characteristics).
The maximum allowable temperature rise (T_Rmax) depends
on the maximum ambient temperature (T_Amax) of the appli-
cation, and the maximum allowable junction temperature
(T_Jmax):
T_Rmax = T_Jmax− T_Amax
The maximum allowable value for junction to ambient Ther-
mal Resistance, θ_JA, can be calculated using the formula:
θ_JA = T_Rmax / P_D
LP3856-ADJ is available in TO-220 and TO-263 packages.
The thermal resistance depends on amount of copper area
or heat sink, and on air flow. If the maximum allowable value
of θ_JA calculated above is ≥ 60 ˚C/W for TO-220 package
and ≥ 60 ˚C/W for TO-263 package no heatsink is needed
since the package can dissipate enough heat to satisfy these
requirements. If the value for allowable θ_JA falls below these
limits, a heat sink is required.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO220 package can be reduced
by attaching it to a heat sink or a copper plane on a PC
board. If a copper plane is to be used, the values of θ_JA will
be same as shown in next section for TO263 package.
The heatsink to be used in the application should have a
heatsink to ambient thermal resistance,
θ_HA≤ θ_JA − θ_CH − θ_JC.
In this equation, θ_CH is the thermal resistance from the case
to the surface of the heat sink and θ_JC is the thermal resis-
tance from the junction to the surface of the case. θ_JC is
about 3˚C/W for a TO220 package. The value for θ_CH de-
pends on method of attachment, insulator, etc. θ_CH varies
between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown,
2˚C/W can be assumed.
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