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LMD18400 Datasheet, PDF (12/18 Pages) National Semiconductor (TI) – Quad High Side Driver
Applications Information (Continued)
Figure 11 indicates the range of load resistance for normal
operation open load and shorted load or power limit indica-
tion
TL H 11026–20
FIGURE 11 Load Resistance Detected as Errors
THERMAL MANAGEMENT
It is particularly important to consider the total amount of
power being dissipated by all four switches in the
LMD18400 at all times Any combination of the switches
driving loads will cause an increase in the die temperature
Should the die temperature reach the thermal shutdown
threshold of a170 C all of the switches will be disabled
Careful calculation of the worst case total power dissipation
required at any point in time together with providing suffi-
cient heatsinking will prevent this from occurring
The LMD18400 is packaged with a special leadframe that
helps dissipate heat through the two ground pins on each
side of the package The thermal resistance from junction-
to-case (iJC) for this package is approximately 20 C W
The thermal resistance from junction-to-ambient (iJA) with-
out any heatsinking is approximately 60 C W Figure 12 il-
lustrates how the copper foil of a printed circuit board can
be designed to provide heatsinking and reduce the overall
junction-to-ambient thermal resistance
The power dissipation in each switch is equal to
PD (Each Switch) e ILoad2 c RON
or
(VCC b VOUT)2
RON
where RON is the ON resistance of the switch (1 3X maxi-
mum) These equations hold true until the power dissipation
reaches the maximum limit of 15W With resistive loads the
15W power limit threshold will be reached when
RL
s
VCC2
60W
Inductive loads will create additional power dissipation when
switched OFF Figure 13 shows the idealized voltage and
current waveforms for an inductive load
Maximum Power Dissipated
and Junction to Ambient
Thermal Resistance vs Size
TL H 11026 – 22
TL H 11026–21
FIGURE 12 Recommended PC Board Layout to Reduce the Thermal Resistance from Junction-to-Ambient
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