LMC6442 Datasheet, PDF (12/16 Pages) National Semiconductor (TI) – Dual Micropower Rail-to-Rail Output Single Supply Operational Amplifier

Applications Information (Continued)
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FIGURE 3. “T” Network Values for Various Values of R
For convenience, Fig. 3 shows R1 vs R_F for different values
of R.
DESIGN CONSIDERATIONS FOR CAPACITIVE LOADS
As with many other opamps, the LMC6442 is more stable at
higher closed loop gains when driving a capacitive load.
Figure 4 shows minimum closed loop gain versus load ca-
pacitance, to achieve less than 10% overshoot in the output
small signal response. In addition, the LMC6442 is more
stable when it provides more output current to the load and
when its output voltage does not swing close to V^−.
The LMC6442 is more tolerant to capacitive loads when the
equivalent output load resistance is lowered or when output
voltage is 1V or greater from the V^− supply. The capacitive
load drive capability is also improved by adding an isolating
resistor in series with the load and the output of the device.
Figure 5 shows the value of this resistor for various capaci-
tive loads (A_V = −1), while limiting the output to less than 10
% overshoot.
Referring to the Typical Performance Characteristics plot of
Phase Margin (Worst Case) vs Supply Voltage, note that
Phase Margin increases as the equivalent output load resis-
tance is lowered. This plot shows the expected Phase Mar-
gin when the device output is very close to V^−, which is the
least stable condition of operation. Comparing this Phase
Margin value to the one read off the Open Loop Gain/Phase
vs Frequency plot, one can predict the improvement in
Phase Margin if the output does not swing close to V^−. This
dependence of Phase Margin on output voltage is minimized
as long as the output load, R_L, is about 1MΩ or less.
Output Phase Reversal: The LMC6442 is immune against
this behavior even when the input voltages exceed the com-
mon mode voltage range.
Output Time Delay: Due to the ultra low power consump-
tion of the device, there could be as long as 2.5 ms of time
delay from when power is applied to when the device output
reaches its final value.
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FIGURE 4. Minimum Operating Gain vs Capactive Load
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10006443
FIGURE 5. Isolating Resistor Value vs Capactive Load
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