CS5530 Datasheet, PDF (12/241 Pages) National Semiconductor (TI) – Geode™ CS5530 I/O Companion Multi-Function South Bridge

2.0 Signal Definitions
This section defines the signals and describes the exter-
nal interface of the Geode CS5530. Figure 2-1 shows the
pins organized by their functional groupings (internal test
and electrical pins are not shown).
CPU Interface
PCI Bus
ROM Interface
Audio Interface
Display: Pixel
Port
Display: CRT
Display: TFT/TV
Display: MPEG
www.national.com
INTR
USBCLK
SMI#
TVCLK
IRQ13
DCLK
PSERIAL
PCICLK
SUSP#
ISACLK
SUSPA#
CLK14_MHZ
SUSP_3V
CLK_32K
HOLD_REQ#
PCI_RST#
AD[31:0]
C/BE[3:0]#
POR#
CPU_RST
INTA#-INTD#
D+_PORT1
REQ#
D–_PORT1
GNT#
D+_PORT2
FRAME#
D–_PORT2
IRDY#
POWER_EN
TRDY#
STOP#
LOCK#
DEVSEL#
PAR
PERR#
SERR#
Geode™ CS5530 ^OVER_CUR#
I/O Companion IDE_ADDR[2:0]
IDE_RST#
Note: Pins that change
function when ISA Master
mode is invoked are repre-
IDE_CS0#
IDE_CS1#
IDE_DREQ0
IDE_DREQ1
KBROMCS#
PC_BEEP
SDATA_OUT
SDATA_IN
SYNC
BIT_CLK
sented with the ISA Mas-
ter Mode function signal
name in parenthesis.
IDE_DACK0#
IDE_DACK1#
IDE_IORDY0
IDE_IORDY1
IDE_IOW0#
IDE_IOW1#
IDE_IOR0#
IDE_IOR1#
PCLK
IDE_DATA[15:0]
PIXEL[23:0]
SA[19:16]
ENA_DISP
(SD[15:0]) SA[15:0]/SD[15:0]
(SA_DIR) SA_LATCH
HSYNC
SBHE#
VSYNC
BALE
HSYNC_OUT
IOCHRDY
VSYNC_OUT
ZEROWS#
DDC_SCL
IOCS16#
DDC_SDA
IOR#
IREF
IOW#
VREF
MEMCS16#
EXTVREFIN
MEMR#
AVDD1-3
AVSS1-5
Analog
MEMW#
AEN
IOUTR
IRQ[15:14], [12:9], [7:3], 1
IOUTG
IRQ8#
IOUTB
DRQ[7:5], [3:0]
DACK#[7:5], [3:0]
FP_DATA17 (MASTER#)
TC
FP_DATA16 (SA_OE#)
SMEMW#/RTCCS#
FP_DATA[15:0] (SA[15:0])
SMEMR#/RTCALE
FP_CLK (No Function)
FP_CLK_EVEN (No Function)
FP_HSYNC_OUT (SMEMW#)
FP_VSYNC_OUT (SMEMR#)
FP_DISP_ENA_OUT (No Function)
FP_ENA_VDD (No Function)
FP_ENA_BKL (No Function)
FP_HSYNC (No Function)
Analog
PLLDVD
PLLVAA
PLLRO
PLLLP
PLLAGS
PLLAGD
PLLDGN
FP_VSYNC (No Function)
GPCS#
GPORT_CS#
VID_DATA[7:0]
(SA[23:20]) GPIO[7:4]/SA[23:20]
VID_RDY
GPIO[3:2]
VID_CLK
GPIO1/SDATA_IN2
VID_VAL
GPIO0
Figure 2-1. CS5530 Signal Groups
12
Clocks
Reset
USB
IDE Controller
ISA Bus
External RTC
DCLKPLL
Game Port/
GPIO
Revision 4.1