SCAN926260_08 Datasheet, PDF (11/20 Pages) National Semiconductor (TI) – Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST

IEEE 1149.1 Test Modes
The SCAN926260 features interconnect test access that is
compliant to the IEEE 1149.1 Standard for Boundary Scan
Test (JTAG). All digital TTL I/O's on the device are accessible
using IEEE 1149.1, and entering this test mode will override
all input control cases including power down and REN. In ad-
dition to the four required Test Access Port (TAP) signals of
TMS, TCK, TDI, and TDO, TRST is provided for test reset.
To supplement the test coverage provided by the IEEE
1149.1 test access to the digital TTL pins, the SCAN926260
has two instructions to test the LVDS interconnects. The first
is EXTEST. This is implemented at LVDS levels and is only
intended as a go no-go test (e.g. missing cables). The second
method is the RUNBIST instruction. It is an "at-system-speed"
interconnect test. It is executed in approximately 33ms with a
system clock speed of 66MHz. There are 12 bits in the RX
BIST data register for notification of PASS/FAIL and
TEST_COMPLETE, with two bits for each of the six channels.
The RX BIST register is defined as (from MSB to LSB):
RX BIST Register
Bit Number
Description
11 (MSB) BIST COMPLETE for Channel 6
10
BIST PASS/FAIL for Channel 6
9
BIST COMPLETE for Channel 5
8
BIST PASS/FAIL for Channel 5
7
BIST COMPLETE for Channel 4
6
BIST PASS/FAIL for Channel 4
5
BIST COMPLETE for Channel 3
4
BIST PASS/FAIL for Channel 3
3
BIST COMPLETE for Channel 2
2
BIST PASS/FAIL for Channel 2
1
BIST COMPLETE for Channel 1
0 (LSB) BIST PASS/FAIL for Channel 1
A "pass" indicates that the BER (Bit-Error-Rate) is better than
10^-7. This is a minimum test, so a "fail" indication means that
the BER is higher than 10^-7.
The BIST features of the SCAN926260 six channel deserial-
izer are compatible with the BIST features on the
BIST Alone Mode Selection
BIST_ACT
1
1
1
1
1
1
1
1
0
BIST_SEL2
0
0
0
0
1
1
1
1
X
BIST_SEL1
0
0
1
1
0
0
1
1
X
DS92LV8028, the SCAN921023 and the SCAN921025 Seri-
alizers.
An important detail is that once both devices have the RUN-
BIST instruction loaded into their respective instruction reg-
isters, both devices must move into the RTI state within 4K
system clocks (At a system CLK of 66MHz and TCK of 1MHz
this allows for 66 TCK cycles). This is not a concern when
both devices are on the same scan chain or LSP. However,
it can be a problem with some multi-drop devices. This test
mode has been simulated and verified using National's En-
hanced SCAN Bridge (SCANSTA111).
BIST Alone Test Modes
The SCAN926260 also supports a BIST Alone feature which
can be run without enabling the JTAG TAP controller. This
feature provides the ability to run continuous BER testing on
all channels, or on individual channels without affecting live
traffic on other channels. The ability to run the BERT (Bit-Er-
ror-Rate-Test) while adjacent channels are carrying normal
traffic is a useful tool to determine how normal traffic will affect
the BER on any given channel.
The BIST Alone features can be accessed using the 5 pins
defined as BIST_SEL0, BIST_SEL1, BIST_SEL2,
BIST_ACT, and BISTMODE_REQ.
BIST_ACT activates the BIST Alone mode. The BIST Alone
mode will continue until deactivated by the BIST_ACT pin.
The BIST_ACT input must be high or low for four or more
clock cycles in order to activate or deactivate the BIST Alone
mode. The BIST_ACT input is pulled low internally.
BISTMODE_REQ is used to select either gross error report-
ing or a specific output error report. When the BIST Alone
mode is active, the LOCKn output for all channels running
BIST Alone will go low and the respective ROUTn(0:9) output
will report any errors. When BISTMODE_REQ is low, the er-
ror reporting is set to Gross Mode, and whenever a bit con-
tains one or more errors, ROUT(0:9) for that channel goes
high and stays high until deactivation by the BIST_ACT input.
When BISTMODE_REQ is high, the output error reporting is
set to Bit Error mode. Whenever any data bit contains an er-
ror, the data output for that corresponding bit goes high. The
default setting is Gross Error mode.
The three BIST_SELn inputs determine which channel is in
BIST Alone mode according to the following table:
BIST_SEL0
0
1
0
1
0
1
0
1
X
BIST for Channel
0
1
2
3
4
5
All Channels
IDLE
IDLE
11
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