SCAN25100_08 Datasheet, PDF (11/34 Pages) National Semiconductor (TI) – 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement

Symbol
Parameter
Condition
Min
JTAG TIMING SPECIFICATIONS
f_JTAG
JTAG TCK Frequency
R_L= 1000Ω, C_L = 15 pF
25
t_R-J
TDO data transition time (20% to
t_F-J
80%)
t_S-TDI
Setup Time TDI to TCK High or Low
2
t_H-TDI
Hold Time TDI to TCK High or Low
2
t_S-TMS
Setup Time TMS to TCK High or
2
Low
t_H-TMS
Hold Time TMS to TCK High or Low
2
t_W-TCK
TCK Pulse Width
10
t_W-TRST
TRSTB Pulse Width
2.5
t_REC
Recovery Time TRSTB to TCK
14
DELAY CALIBRATION MEASUREMENT (DCM) (Notes 12, 14, 15)
T₁₄
T_offset
T_ser
T_des
T_in-out
T_out-in
T₁₄ Delay Accuracy
T_offset Delay Accuracy
Serializer Delay Accuracy
Deserializer Delay Accuracy
T_in-out Delay Accuracy
T_out-in Delay Accuracy
Receive and Transmit PLLs locked
to valid hyperframe data.
Typ
(Note 2)
Max
2
± 800
± 800
± 1200
± 1200
± 1200
± 1200
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Typical parameters are measured at nominal supply levels and T_A = 25°C. They are for reference purposes and are not production-tested.
Note 3: Transmit Jitter testing methodology is defined in Appendix 48B of IEEE 802.2ae-2002. The SCAN25100 transmit output jitter is constant for all valid CPRI
datarates. For 614.4 and 1228.8 Mbps rates, the transmit jitter is significantly less than the specified limits in terms of UI.
Note 4: CJPAT is a stress pattern defined in IEEE 802.2ae-2002 Appendix 48A
Note 5: CDET nominal valid duration is determined by the CPRI data rate. CDET timing is similar to the ROUT[0:9] timing.
Note 6: Transmit or Receive K28.5 pattern. Assumes TXCLK is stable and toggles only after all SerDes clocks become synchronous.
Note 7: Conditions: The TX PLL is locked, the TXCLK is stable and the TXCLK is synchronous.
Note 8: Transmit latency is fixed once the link is established and is guaranteed by the Tser specification.
Note 9: Receive latency is fixed once the link is established and is guaranteed by the Tdes specification.
Note 10: Conditions: The RX PLL is locked to the incoming data and the SCAN25100 is in WRITE mode.
Note 11: Receiver output timing specifications for TS-R and TH-R are tested at the CPRI rate of 2.4576 Gbps.
Note 12: Limits are guaranteed by design and characterization over process, supply voltage, and temperature variations.
Note 13: Limits are guaranteed by design.
Note 14: Serial side DCM readings are referenced to the first bit of the K28.5 pattern {110000 0101 001111 1010}. Parallel side DCM readings are referenced
to the TXCLK or RXCLK edge (not the data edge) that registers the K character as an input or output.
Note 15: DCM readings have been validated when the RXCLK pin on the SCAN25100 is used as an output in "WRITE" mode (RXCLKMODE = 0) and IOVDD
= 3.3V.
Note 16: Edge rate characterization includes the loading effects of 1.0 uF AC-coupling capacitors and 4 inches of 100-Ohm differential microstrip.
11
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