DS90CF364A_07 Datasheet, PDF (11/18 Pages) National Semiconductor (TI) – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65MHz

DS90CF384A Pin Descriptions — 56L TSSOP Package — 24-Bit FPD Link
Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
Description
I 4 Positive LVDS differentiaI data inputs.
I 4 Negative LVDS differential data inputs.
O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
I 1 Positive LVDS differential clock input.
I 1 Negative LVDS differential clock input.
O 1 TTL Ievel clock output. The falling edge acts as data strobe.
I 1 TTL level input. When asserted (low input) the receiver outputs are low.
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
I 1 Power supply for PLL.
I 2 Ground pin for PLL.
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
DS90CF364A Pin Descriptions — 48L TSSOP Package — 18-Bit FPD Link
Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
Description
I 3 Positive LVDS differentiaI data inputs.
I 3 Negative LVDS differential data inputs.
O 21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
I 1 Positive LVDS differential clock input.
I 1 Negative LVDS differential clock input.
O 1 TTL Ievel clock output. The falling edge acts as data strobe.
I 1 TTL level input. When asserted (low input) the receiver outputs are low.
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
I 1 Power supply for PLL.
I 2 Ground pin for PLL.
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
11
www.national.com