LP38513 Datasheet, PDF (10/14 Pages) National Semiconductor (TI) – 3A Fast Response Ultra Low Dropout Linear Regulator

on/off cycling to a lower frequency. Please refer to the POW-
ER DISSIPATION/HEAT-SINKING section for power dissi-
pation calculations.
ENABLE OPERATION
The Enable On/Off threshold is typically 850 mV, and has no
hysteresis. The voltage signal must rise and fall cleanly, and
promptly, through this threshold.
The Enable pin (EN) has no internal pull-up or pull-down to
establish a default condition and, as a result, this pin must be
terminated either actively or passively.
If the Enable pin is driven from a single ended device (such
as the collector of a discrete transistor) a pull-up resistor to
V_IN, or a pull-down resistor to ground, will be required for
proper operation. A 1 kΩ to 100 kΩ resistor can be used as
the pull-up or pull-down resistor to establish default condition
for the EN pin. The resistor value selected should be appro-
priate to swamp out any leakage in the external single ended
device, as well as any stray capacitance.
If the Enable pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator output), the
pull-up, or pull-down, resistor is not required.
If the application does not require the Enable function, the pin
should be connected directly to the adjacent V_IN pin.
The status of the Enable pin also affects the behavior of the
ERROR Flag. While the Enable pin is high the regulator con-
trol loop will be active and the ERROR Flag will report the
status of the output voltage. When the Enable pin is taken low
the regulator control loop is shutdown, the output is turned off,
and the internal logic will immediately force the ERROR Flag
pin low.
ERROR FLAG OPERATION
When the LP38513 Enable pin is high, the ERROR Flag pin
will produce a logic low signal when the output drops by more
than 15% (V_TH, typical) from the nominal output voltage. The
drop in output voltage may be due to low input voltage, current
limiting, or thermal limiting. This flag has a built in hysteresis.
The output voltage will need to rise to greater than typically
89% of the nominal output voltage for the ERROR Flag to
return to a logic high state. It should also be noted that when
the Enable pin is pulled low, the ERROR Flag pin is forced to
be low as well.
The internal ERROR flag comparator has an open drain out-
put stage. Hence, the ERROR pin requires an external
pull-up resistor. The value of the pull-up resistor should be in
the range of 2 kΩ to 20 kΩ, and should be connected to the
LP38513 output voltage pin. The ERROR Flag pin should not
be pulled-up to any voltage source higher than V_IN as current
flow through an internal parasitic diode may cause unexpect-
ed behavior. When the input voltage is less than typically
1.25V the status of the ERROR flag output will not be reliable.
The ERROR Flag pin must be connected to ground if this
function is not used.
The timing diagram in Figure 1 shows the relationship be-
tween the ERROR flag and the output voltage when the pull-
up resistor is connected to the output voltage pin.
The timing diagram in Figure 2 shows the relationship be-
tween the ERROR flag and the output voltage when the pull-
up resistor is connected to the input voltage.
FIGURE 1. ERROR Flag Operation, see Typical Application
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