LMX2531LQ1500E Datasheet, PDF (10/23 Pages) National Semiconductor (TI) – High Performance Frequency Synthesizer System with Integrated VCO

1.0 Functional Description (Continued)
tuning gain, and therefore better phase noise performance.
The frequency calibration routine is activated any time that
the R0 register is programmed. If the temperature shifts
considerably and the R0 register is not programmed, then it
can not drift more than the maximum allowable drift for
continuous lock, ∆T_CL, or else the VCO is not guaranteed to
stay in lock. The phase noise calibration algorithm is neces-
sary in order to achieve the lowest possible phase noise.
The VCO_ACI_SEL bit ( R6[19:16] ) needs to be set to the
correct value to ensure the best possible phase noise.
The gain of the VCO can change considerably over fre-
quency. It is lowest at the minimum frequency and highest at
the maximum frequency. This range is specified in the
datasheet. When designing the loop filter, the following
method is recommended. First, take the geometric mean of
the minimum and maximum frequencies that are to be used.
Then use a linear approximation to extrapolate the VCO
gain.
1.7 PROGRAMMABLE DIVIDE BY 2
All options of the LMX2531LQ1500E offer a divide by 2
option. This allows the user to get exactly half of the VCO
frequency, by dividing the output of the VCO output by two.
Because this divide by two is outside feedback path between
the VCO and the PLL, the loop filter and counter values are
set up for the VCO frequency before it is divide by two. Note
that R0 register should be reprogrammed the first time after
the DIV2 bit is enabled or disabled for optimal phase noise
performance.
1.8 CHOOSING THE CHARGE PUMP CURRENT AND
COMPARISON FREQUENCY
The LMX2531LQ1500E has 16 levels of charge pump cur-
rents and a highly flexible fractional modulus. This gives the
user many degrees of freedom. This section discusses some
of the design considerations. From the perspective of the
PLL noise, choosing the charge pump current and compari-
son frequency as high as possible are best for optimal phase
noise performance. The far out PLL noise improves 3 dB for
every doubling of the comparison frequency, but at lower
offsets, this effect is much less due to the PLL 1/f noise.
Increasing the charge pump current improves the phase
noise about 3 dB per doubling of the charge pump current,
although there are small diminishing returns as the charge
pump current goes higher.
From a loop filter design and PLL phase noise perspective,
one might think to always design with the highest possible
comparison frequency and charge pump current. However, if
one considers the worst case fractional spurs that occur at
an output frequency equal to 1 channel spacing away from a
multiple of the OSCin frequency, then this gives reason to
reconsider. If the comparison frequency or charge pump
currents are too high, then these spurs could be degraded,
and the loop filter may not be able to filter these spurs as well
as theoretically predicted. For optimal spur performance, a
comparison frequency in the ballpark of 2.5 MHz and a
charge pump current of 1X are recommended.
www.national.com
10