LMX2525 Datasheet, PDF (10/17 Pages) National Semiconductor (TI) – PLLatinum Dual Frequency Synthesizer System with Integrated VCOs

Functional Description (Continued)
BAND SELECT MODE
The BS pin and BS bit can be used to select one of the two
RF VCO outputs. When using the BS pin, the BS bit must be
set to 0, and when using the BS bit, the BS pin must be tied
to ground. When using the BS pin, the state of the input must
exceed the minimum band select set up time prior to the LE
signal transition. The truth table summarizing the band select
logic is as follows:
TABLE 2. Band Select Modes
BS Pin
HIGH
LOW
LOW
BS Bit
0
0
1
Mode
PDC1500
PDC800
PDC1500
LOCK DETECT MODE
The LD output can be used to indicate the lock status of the
PLL. Bit 6 in Register R1 determines the signal that appears
on the LD pin. When the PLL is not locked, the LD pin
remains LOW. After obtaining phase lock, the LD pin will
have a logical HIGH level. The LD output is always LOW
when the LD register bit is 0 and in power down mode.
TABLE 3. Lock Detect Modes
LD Bit
0
1
Mode
Disable (GND)
Enable
TABLE 4. Lock Detect Logic
RF PLL Section
Locked
Not Locked
LD Output
HIGH
LOW
FIGURE 2. Lock Detect Timing Diagram Waveform (Notes 15, 16, 17, 18, 19)
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Note 15: LD output becomes LOW when the phase error is larger than t_W2.
Note 16: LD output becomes HIGH when the phase error is less than t_W1 for
four or more consecutive cycles.
Note 17: Phase Error is determined on the leading edge. Only errors greater
than t_W1 and t_W2 are labeled.
Note 18: t_W1 is 5 ns for PDC1500 and 10 ns for PDC800. t_W2 is 10 ns for
both bands.
Note 19: The lock detect comparison occurs with every 64^th cycle of f_R and
f_N.
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