ADC1173 Datasheet, PDF (10/17 Pages) National Semiconductor (TI) – 8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter

Functional Description
The ADC1173 uses a new, unique architecture to achieve
7.4 effective bits at and maintains superior dynamic perfor-
mance up to ¹â„2 the clock frequency.
The analog signal at V_IN that is within the voltage range set
by V_RT and V_RB are digitized to eight bits at up to 20 MSPS.
Input voltages below V_RB will cause the output word to con-
sist of all zeroes. Input voltages above V_RT will cause the
output word to consist of all ones. V_RT has a range of 1.0 Volt
to the analog supply voltage, AV_DD, while V_RB has a range of
0 to 2.0 Volts. V_RT should always be at least 1.0 Volt more
positive than V_RB.
If V_RT and V_RTS are connected together and V_RB and V_RBS
are connected together, the nominal values of V_RT and V_RB
are 1.56V and 0.36V, respectively. If V_RT and V_RTS are con-
nected together and V_RB is grounded, the nominal value of
V_RT is 1.38V.
Data is acquired at the falling edge of the clock and the digi-
tal equivalent of the data is available at the digital outputs 2.5
clock cycles plus t_OD later. The ADC1173 will convert as long
as the clock signal is present at pin 12. The Output Enable
pin OE, when low, enables the output pins. The digital out-
puts are in the high impedance state when the OE pin is
high.
Applications Information
1.0 The Analog Input
The analog input of the ADC1173 is a switch followed by an
integrator. The input capacitance changes with the clock
level, appearing as 4 pF when the clock is low, and 11 pF
when the clock is high. Since a dynamic capacitance is more
difficult to drive than a fixed capacitance, choose an amplifier
that can drive this type of load. The CLC409, CLC440,
LM6152, LM6154, LM6181 and LM6182 have been found to
be excellent devices for driving the ADC1173. Do not drive
the input beyond the supply rails.
Figure 3 shows an example of an input circuit using the
LM6181. This circuit has both gain and offset adjustments. If
you desire to eliminate these adjustments, you should re-
duce the signal swing to avoid clipping at the ADC1173 out-
put that can result from normal tolerances of all system com-
ponents. With no adjustments, the nominal value for the
amplifier feedback resistor is 510Ω and the 5.1k resistor at
the inverting input should be changed to 860Ω and returned
to +3V rather than to the Offset Adjust potentiometer.
2.0 Reference Inputs
The reference inputs V_RT (Reference Top) and V_RB (Refer-
ence Bottom) are the top and bottom of the reference ladder.
Input signals between these two voltages will be digitized to
8 bits. External voltages applied to the reference input pins
should be within the range specified in the Operating Ratings
table (1.0V to AV_DD for V_RT and 0V to (AV_DD - 1.0V) for V_RB).
Any device used to drive the reference pins should be able to
source sufficient current into the V_RT pin and sink sufficient
current from the V_RB pin.
The reference ladder can be self-biased by connecting V_RT
to V_RTS and connecting V_RB to V_RBS to provide top and bot-
tom reference voltages of approximately 1.56V and 0.36V,
respectively, with V_CC = 3.0V. This connection is shown in
Figure 3. If V_RT and V_RTS are tied together, but V_RB is tied to
analog ground, a top reference voltage of approximately
1.38V is generated. The top and bottom of the ladder should
be bypassed with 10µF tantalum capacitors located close to
the reference pins.
The reference self-bias circuit of Figure 3 is very simple and
performance is adequate for many applications. Superior
performance can generally be achieved by driving the refer-
ence pins with a low impedance source.
By forcing a little current into or out of the top and bottom of
the ladder, as shown in Figure 4, the top and bottom refer-
ence voltages can be trimmed. The resistive divider at the
amplifier inputs can be replaced with potentiometers. The
LMC662 amplifier shown was chosen for its low offset volt-
age and low cost. Note that a negative power supply is
needed for these amplifiers as their outputs may be required
to go slightly negative to force the required reference
voltages.
www.national.com
10