TP3410 Datasheet, PDF (1/32 Pages) National Semiconductor (TI) – TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver

September 1994
TP3410 ISDN Basic Access
Echo-Cancelling 2B1Q U Transceiver
General Description
The TP3410 is a complete monolithic transceiver for ISDN
Basic Access data transmission at either end of the U inter-
face Fully compatible with ANSI specification T1 601 it is
built on National’s advanced double-metal CMOS process
and requires only a single a5V power supply A total of
160 kbps full-duplex transmission on a single twisted-pair is
provided with user-accessible channels including 2 ‘B’
channels each at 64 kbps 1 ‘D’ channel at 16 kbps and an
additional 4 kbps for loop maintenance 12 kbps of band-
width is reserved for framing 2B1Q Line coding is used in
which pairs of binary bits are coded into 1 of 4 quantum
levels for transmission at 80k symbols sec (hence 2 Binary
1 Quaternary) To meet the very demanding specifications
for ^k1 in 10e7 Bit Error Rate even on long loops with cross-
talk the device includes 2 Adaptive Digital Signal Proces-
sors 2 Digital Phase-locked Loops and a controller for auto-
matic activation
The digital interface on the device can be programmed for
compatibility with either of two types of control interface for
chip control and access to all spare bits In one mode a
Microwire serial control interface is used together with a
2BaD digital interface which is compatible with the Time-di-
vision Multiplexed format of PCM Combo devices and back-
planes This mode allows independent time-slot assignment
for the 2 B channels and the D channel
Alternatively the GCI (General Circuit Interface) may be se-
lected in which the 2BaD data is multiplexed together with
control spare bits and loop maintenance data on 4 pins
Combo and TRI-STATE are registered trademarks of National Semiconductor Corporation
MICROWIRETM is a trademark of National Semiconductor Corporation
The General Circuit Interface (G C I ) is an interface specification of the Group-of-Four Euro-
pean Telecommunications Companies
Features
Y _{2 ‘B’}a_{‘D’ channel 160 kbps transceiver for LT and NT}
Y _{Meets ANSI T1 601 U S Standard}
Y _{2B1Q line coding with scrambler descrambler}
Y _{Range exceeds 18 kft of 26 AWG}
Y l_{70 dB adaptive echo-cancellation and equalization}
Y _{On-chip timing recovery no precision external}
components
Y _{Direct connection to small line transformer}
Y _{Automatic activation controller}
Y _{Selectable digital interface formats}
TDM with time-slot assigner up to 64 slots plus
MICROWIRE^TM control interface
GCI (General Circuit Interface) or
IDL (Inter-chip Digital Link)
Y _{Backplane clock DPLL allows free-running XTAL}
Y _{Elastic data buffers meet Q 502 wander jitter for Slave-}
slave mode on PBX Trunk Cards and DLC
Y _{EOC and spare bits access with automatic validation}
Y _{Block error counter}
Y _{6 loopback test modes}
Y _Single a_{5V supply 325 mW active power}
Y _{20 mW idle mode with line signal ‘‘wake-up’’ detector}
Applications
Y _{LT NT-1 NT-2 Trunks U-TE’s Regenerators etc}
Y _{Digital Loop Carrier}
Y _{POTS Pair-Gain Systems}
Y _{Easy Interface to}
Line Card Backplanes
‘‘S’’ Interface Device
Codec Filter Combos
TP3420A
TP3054 7 and TP3075 6
LAPD Processor
HDLC Controller
MC68302 HPC16400
TP3451
Block Diagram
Note Pin names show Microwire mode
C1995 National Semiconductor Corporation TL H 9151
TL H 9151 – 1
RRD-B30M115 Printed in U S A