SCANSTA111_05 Datasheet, PDF (1/31 Pages) National Semiconductor (TI) – Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port

October 2005
SCANSTA111
Enhanced SCAN bridge
Multidrop Addressable IEEE 1149.1 (JTAG) Port
General Description
The SCANSTA111 extends the IEEE Std. 1149.1 test bus
into a multidrop test bus environment. The advantage of a
multidrop approach over a single serial scan chain is im-
proved test throughput and the ability to remove a board
from the system and retain test access to the remaining
modules. Each SCANSTA111 supports up to 3 local
IEEE1149.1 scan rings which can be accessed individually
or combined serially. Addressing is accomplished by loading
the instruction register with a value matching that of the Slot
inputs. Backplane and inter-board testing can easily be ac-
complished by parking the local TAP Controllers in one of the
stable TAP Controller states via a Park instruction. The 32-bit
TCK counter enables built in self test operations to be per-
formed on one port while other scan chains are simulta-
neously tested.
Features
n True IEEE 1149.1 hierarchical and multidrop
addressable capability
n The 7 slot inputs support up to 121 unique addresses,
an Interrogation Address, Broadcast Address, and 4
Multi-cast Group Addresses (address 000000 is
reserved)
n 3 IEEE 1149.1-compatible configurable local scan ports
n Mode Register₀ allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or
serially in groups of two or three
n Transparent Mode can be enabled with a single
instruction to conveniently buffer the backplane IEEE
1149.1 pins to those on a single local scan port
n LSP ACTIVE outputs provide local port enable signals
for analog busses supporting IEEE 1149.4.
n General purpose local port passthrough bits are useful
for delivering write pulses for FPGA programming or
monitoring device status.
n Known Power-up state
n TRST on all local scan ports
n 32-bit TCK counter
n 16-bit LFSR Signature Compactor
n Local TAPs can become TRI-STATE via the OE input to
allow an alternate test master to take control of the local
TAPs (LSP_0-2 have a TRI-STATE notification output)
n 3.0-3.6V V_CC Supply Operation
n Power-off high impedance inputs and outputs
n Supports live insertion/withdrawal
Connection Diagrams
10124502
© 2005 National Semiconductor Corporation DS101245
10124516
www.national.com