SCAN92LV090_06 Datasheet, PDF (1/14 Pages) National Semiconductor (TI) – 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

December 2006
SCAN92LV090
9 Channel Bus LVDS Transceiver w/ Boundary SCAN
General Description
The SCAN92LV090A is one in a series of Bus LVDS
transceivers designed specifically for the high speed, low
power proprietary backplane or cable interfaces. The device
operates from a single 3.3V power supply and includes nine
differential line drivers and nine receivers. To minimize bus
loading, the driver outputs and receiver inputs are internally
connected. The separate I/O of the logic side allows for loop
back support. The device also features a flow through pin out
which allows easy PCB routing for short stubs between its
pins and the connector.
The driver translates 3V TTL levels (single-ended) to differ-
ential Bus LVDS (BLVDS) output levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition, the differential signaling provides
common mode noise rejection of ±1V.
The receiver threshold is less than ±100 mV over a ±1V com-
mon mode range and translates the differential Bus LVDS to
standard (TTL/CMOS) levels.
This device is compliant with IEEE 1149.1 Standard Test Ac-
cess Port and Boundary Scan Architecture with the incorpo-
ration of the defined boundary-scan test logic and test access
port consisting of Test Data Input (TDI), Test Data Out (TDO),
Test Mode Select (TMS), Test Clock (TCK), and the optional
Test Reset (TRST).
Features
■ ^{IEEE 1149.1 (JTAG) Compliant}
■ ^{Bus LVDS Signaling}
■ ^{Low power CMOS design}
■ ^{High Signaling Rate Capability (above 100 Mbps)}
■ ^{0.1V to 2.3V Common Mode Range for V}_ID ^{= 200mV}
■ ^{±100 mV Receiver Sensitivity}
■ ^{Supports open and terminated failsafe on port pins}
■ ^{3.3V operation}
■ ^{Glitch free power up/down (Driver & Receiver disabled)}
■ ^{Light Bus Loading (5 pF typical) per Bus LVDS load}
■ ^{Designed for Double Termination Applications}
■ ^{Balanced Output Impedance}
■ ^{Product offered in 64 pin LQFP package and BGA}
package
■ ^{High impedance Bus pins on power off (V}_CC ^{= 0V)}
Simplified Functional Diagram
Connection Diagrams
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