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SCAN25100_0611 Datasheet, PDF (1/14 Pages) National Semiconductor (TI) – 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement | |||
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November 2006
SCAN25100
2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE
Sync and Precision Delay Calibration Measurement
General Description
The SCAN25100 is a 2457.6, 1228.8, and 614.4 Mbps seri-
alizer/deseralizer (SerDes) for high-speed bidirectional serial
data transmission over FR-4 printed circuit board backplanes,
balanced cables, and optical fiber. The SCAN25100 inte-
grates precision delay calibration measurement (DCM) cir-
cuitry that measures link delay components to better than ±
800 ps accuracy.
The SCAN25100 features independent transmit and receive
PLLs, on-chip oscillator, and intelligent clock management
circuitry to automatically perform remote radio head synchro-
nization and reduce the cost and complexity of external clock
networks.
The SCAN25100 is programmable though an MDIO interface
as well as through pins, featuring configurable transmitter de-
emphasis, receiver equalization, speed rate selection, inter-
nal pattern generation/verification, and loop back modes. In
addition to at-speed BIST, the SCAN25100 includes IEEE
1149.1 and 1149.6 testability.
Note: For a full datasheet of the SCAN25100 please con-
tact your local National Semiconductor representitive.
Features
â Exceeds LV and HV CPRI voltage and jitter requirements
â 2457.6, 1228.8, and 614.4 Mbps operation
â Integrated delay calibration measurement (DCM) directly
measures T14 and Toffset delays to ⤠± 800 ps
â DCM also measures chip and other delays to ⤠± 1200 ps
accuracy
â Deterministic chip latency
â Automatic receiver lock and RE synchronization without
reference clock or external crystal
â Independent transmit and receive PLLs for seamless RE
synchronization
â Low noise recovered clock output
â Requires no jitter cleaning in single-hop applications
â >8 kV ESD on the CML IO, >7 kV on all other pins, >2 kV
CDM
â Hot plug protection
â LOS, LOF, 8b/10b line code violation, comma, and
receiver PLL lock reporting
â Programmable hyperframe length and start of hyperframe
character
â Programmable transmit de-emphasis and receive
equalization with on-chip termination
â Advanced testability features
â IEEE 1149.1 and 1149.6
â At-speed BIST pattern generator/verifier
â Multiple loopback modes
â 1.8V or 3.3V compatible parallel bus interface
â 100-pin TQFP package with exposed dap
â Industrial â40 to +85° C temperature range
Block Diagram
© 2006 National Semiconductor Corporation 201834
20183442
www.national.com
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