SCAN25100 Datasheet, PDF (1/3 Pages) National Semiconductor (TI) – 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement

PRELIMINARY
September 2006
SCAN25100
2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto
RE Sync and Precision Delay Calibration Measurement
General Description
The SCAN25100 is a 2457.6, 1228.8, and 614.4 Mbps
serializer/deseralizer (SerDes) for high-speed bidirectional
serial data transmission over FR-4 printed circuit board
backplanes, balanced cables, and optical fiber. The
SCAN25100 integrates precision delay calibration measure-
ment (DCM) circuitry that measures link delay components
to better than ± 800 ps accuracy.
The SCAN25100 features independent transmit and receive
PLLs, on-chip oscillator, and intelligent clock management
circuitry to automatically perform remote radio head synchro-
nization and reduce the cost and complexity of external clock
networks.
The SCAN25100 is programmable though an MDIO inter-
face as well as through pins, featuring configurable transmit-
ter de-emphasis, receiver equalization, speed rate selection,
internal pattern generation/verification, and loop back
modes. In addition to at-speed BIST, the SCAN25100 in-
cludes IEEE 1149.1 and 1149.6 testability.
Features
n Exceeds LV and HV CPRI voltage and jitter
requirements
n 2457.6, 1228.8, and 614.4 Mbps operation
n Integrated delay calibration measurement (DCM) directly
measures T14 and Toffset delays to ≤ ± 800 ps
n DCM also measures chip and other delays to ≤ ± 1200
ps accuracy
n Deterministic chip latency
n Automatic receiver lock and RE synchronization without
reference clock or external crystal
n Independent transmit and receive PLLs for seamless RE
synchronization
n Low noise recovered clock output
n Requires no jitter cleaning in single-hop application
n >8 kV ESD on the CML IO, >7 kV on all other pins, >2
kV CDM
n Hot plug protection
n LOS, LOF, 8b/10b line code violation, comma, and
receiver PLL lock reporting
n Programmable hyperframe length and start of
hyperframe character
n Programmable transmit de-emphasis and receive
equalization with on-chip termination
n Advanced testability features
— IEEE 1149.1 and 1149.6
— At-speed BIST pattern generator/verifier
— Multiple loopback modes
n 1.8V or 3.3V compatible parallel bus interface
n 100-pin TQFP package with exposed dap
n Industrial –40 to +85˚ C temperature range
Block Diagram
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