MM54HCT147 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – 10-to-4 Line Priority Encoder

PRELIMINARY
November 1995
MM54HCT147 MM74HCT147
10-to-4 Line Priority Encoder
General Description
This priority encoder utilizes advanced silicon-gate CMOS
technology It has the high noise immunity and low power
consumption typical of CMOS circuits as well as the speeds
and output drive similar to LS-TTL
This priority encoder accepts 9 input request lines 1– 9 and
outputs 4 line BCD The priority encoding ensures that only
the highest order data line is encoded The implied decimal
zero condition requires no input condition as zero is encod-
ed when all nine data lines are at a high logic level All data
inputs and outputs are active at low logic level
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V_CC and ground
MM54HCT MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices These parts are also plug in replacements for LS-
TTL devices and can be used to reduce power comsump-
tion in existing designs
Features
Y _{Low quiescent power consumption}
40 mW maximum at 25 C
Y _{High speed 13 ns propagation delay (typical)}
Y _{Very low input current 10}^b5 _{mA typical}
Connection and Logic Diagrams
Dual-In-Line Package
TL F 9397 – 1
Order Number MM54HCT147 or MM74HCT147
Truth Table
Inputs
Outputs
1 2 3 4 5 6 7 8 9DCBA
HHHHHHHHHHHHH
XXXXXXXX L LHHL
XXXXXXX LHLHHH
XXXXXX LHHHL L L
XXXXX LHHHHL LH
XXXX LHHHHHLHL
XXX LHHHHHHLHH
XX LHHHHHHHHL L
X LHHHHHHHHHLH
L HHHHHHHHHHH L
H e High Logic Level L e Low Logic Level X e Irrelevant
C1995 National Semiconductor Corporation TL F 9397
TL F 9397 – 2
RRD-B30M115 Printed in U S A