MM54C32 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – Quad 2-Input OR Gate

MM54C32 MM74C32 Quad 2-Input OR Gate
General Description
Employing complementary MOS (CMOS) transistors to
achieve low power and high noise margin these gates pro-
vide the basic functions used in the implementation of digital
integrated circuit systems The N- and P-channel enhance-
ment mode transistors provide a symmetrical circuit with
output swings essentially equal to the supply voltage This
results in high noise immunity over a wide supply voltage
range No DC power other than that caused by leakage cur-
rent is consumed during static conditions All inputs are pro-
tected against static discharge damage
Features
Y _{Wide supply voltage range}
Y _{Guaranteed noise margin}
Y _{High noise immunity}
Y _{Low power}
TTL compatibility
Connection Diagram
Dual-In-Line Package
February 1988
3 0V to 15V
1 0V
0 45V V_CC (typ )
fan out of 2
driving 74L
Top View
Order Number MM54C32 or MM74C32
TL F 5881 – 1
C1995 National Semiconductor Corporation TL F 5881
RRD-B30M105 Printed in U S A