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LMK03200 Datasheet, PDF (1/40 Pages) National Semiconductor (TI) – Precision 0-Delay Clock Conditioner with Integrated VCO | |||
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LMK03200 Family
August 20, 2009
Precision 0-Delay Clock Conditioner with Integrated VCO
General Description
The LMK03200 family of precision clock conditioners com-
bine the functions of jitter cleaning/reconditioning, multiplica-
tion, and 0-delay distribution of a reference clock. The devices
integrate a Voltage Controlled Oscillator (VCO), a high per-
formance Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, and up to eight outputs in various LVDS
and LVPECL combinations.
The VCO output is optionally accessible on the Fout port. In-
ternally, the VCO output goes through a VCO divider to feed
the various clock distribution blocks.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
The PLL also features delay blocks to permit global phase
adjustment of clock output phase. This allows multiple inte-
ger-related and phase-adjusted copies of the reference to be
distributed to eight system components.
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
Target Applications
â Data Converter Clocking
â Networking, SONET/SDH, DSLAM
â Wireless Infrastructure
â Medical
â Test and Measurement
â Military / Aerospace
Features
â Integrated VCO with very low phase noise floor
â Integrated Integer-N PLL with outstanding normalized
phase noise contribution of -224 dBc/Hz
â VCO divider values of 2 to 8 (all divides)
â Bypassable with VCO Mux when not in 0-delay mode
â Channel divider values of 1, 2 to 510 (even divides)
â LVDS and LVPECL clock outputs
â Partially integrated loop filter
â Dedicated divider and delay blocks on each clock output
â 0-delay outputs
â Internal or external feedback of output clock
â Delay blocks on N and R phase detector inputs for lead/
lag global skew adjust
â Pin compatible family of clocking devices
â 3.15 to 3.45 V operation
â Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
â 200 fs RMS Clock generator performance (10 Hz to 20
MHz) with a clean input clock
Device
LMK03200
Outputs
3 LVDS
5 LVPECL
VCO
Tuning Range RMS Jitter
(MHz)
(fs)
1185 - 1296
800
System Diagram
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© 2009 National Semiconductor Corporation 300887
30088740
www.national.com
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