FPD87392AXA Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS™ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA)

PRELIMINARY
July 2003
FPD87392AXA
+3.3V TFT-LCD Timing Controller with Dual LVDS
Inputs/Dual RSDS^™ Outputs for TFT-LCD Monitor and
Notebook (SXGA/SXGA+/UXGA)
General Description
The FPD87392AXA Panel Timing Controller is an integrated
FPD-Link + RSDS™ + TFT-LCD Timing Controller. The logic
architecture is implemented using standard and default tim-
ing controller functionality based on an Embedded Gate
Array. The device is reconfigurable to the needs of a specific
application by providing user-defined specifications or cus-
tomer supplied VHDL/Verilog code.
The FPD87392AXA is a timing controller that combines an
LVDS dual pixel input interface with National’s Reduced
Swing Differential Signaling (RSDS™) output column driver
interface for SXGA, SXGA+ and UXGA resolutions. It re-
sides on the TFT-LCD panel and provides the data buffering
and control signal generation. The RSDS™ data path to the
column driver contributes toward lowering radiated EMI and
reduced system dynamic power consumption. The RSDS™
dual 12 pair differential bus conveys up to 24-bit color data
for SXGA/SXGA+/UXGA panels when using VESA 60Hz
standard timing.
Features
n Input frequency range from 30 MHz to 85 MHz
n Support display resolutions SXGA (1280x1024), SXGA+
(1400x1050) and UXGA (1600x1200)
n Embedded gate array for custom panel timing
n RSDS™ (Reduced Swing Differential Signaling) Column
Driver bus for low power and reduced EMI
n Drives RSDS™ column driver up to 170 Mb/s with an 85
MHz clock
n 6 or 8 bit LVDS dual pixel input interface (FPD-Link)
n Virtual 8-bit color depth in FRC mode
n Flexible RSDS™ data output mapping for Bottom or Top
mount
n Supports 1 and 2 line inversion mode for RVS output
n Supports Graphics Controllers with spread spectrum
interface for lower EMI
n Free Run Mode Function
n Fail-safe function in DE mode (Bonding Option)
n Supports DE mode and SYNC only mode (Bonding
Option)
n Power-On-Reset Support
n CMOS circuitry operates from a 2.7V to 3.6V supply
n Operation frequency: 54 MHz (max) @ V_CC: 2.7 ∼ 3.0V
n Operation frequency: 85 MHz (max) @ V_CC: 3.0 ∼ 3.6V
n 128 TQFP package with body size 14mm x 14mm x
1.0mm, 0.4mm Pitch
© 2003 National Semiconductor Corporation DS200750
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