DS99R105 Datasheet, PDF (1/24 Pages) National Semiconductor (TI) – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

October 2007
DS99R105/DS99R106
3-40MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS99R105/DS99R106 Chipset translates a 24-bit paral-
lel bus into a fully transparent data/control LVDS serial stream
with embedded clock information. This single serial stream
simplifies transferring a 24-bit bus over PCB traces and cable
by eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths that
in turn reduce PCB layers, cable width, and connector size
and pins.
The DS99R105/DS99R106 incorporates LVDS signaling on
the high-speed I/O. LVDS provides a low power and low noise
environment for reliably transferring data over a serial trans-
mission path. By optimizing the serializer output edge rate for
the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects.
Features
■ ^{3 MHz–40 MHz clock embedded and DC-Balancing 24:1}
and 1:24 data transmissions
■ ^{Capable to drive shielded twisted-pair cable}
■ ^{User selectable clock edge for parallel data on both}
Transmitter and Receiver
■ ^{Internal DC Balancing encode/decode – Supports AC-}
coupling interface with no external coding required
■ ^{Individual power-down controls for both Transmitter and}
Receiver
■ ^{Embedded clock CDR (clock and data recovery) on}
Receiver and no external source of reference clock
needed
■ ^{All codes RDL (random data lock) to support live-}
pluggable applications
■ ^{LOCK output flag to ensure data integrity at Receiver side}
■ ^{Balanced T}_SETUP^/T_HOLD ^{between RCLK and RDATA on}
Receiver side
■ ^{PTO (progressive turn-on) LVCMOS outputs to reduce}
EMI and minimize SSO effects
■ ^{All LVCMOS inputs and control pins have internal}
pulldown
■ ^{On-chip filters for PLLs on Transmitter and Receiver}
■ ^{Integrated 100Ω input termination on Receiver}
■ ^{4 mA Receiver output drive}
■ ^{48-pin TQFP and 48-pin LLP packages}
■ ^{Pure CMOS .35 μm process}
■ ^{Power supply range 3.3V ± 10%}
■ ^{Temperature range 0°C to +70°C}
■ ^{8 kV HBM ESD tolerance}
Block Diagram
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation 202081
20208101
www.national.com