DS92LV090A Datasheet, PDF (1/9 Pages) National Semiconductor (TI) – 9 Channel Bus LVDS Transceiver

April 2000
DS92LV090A
9 Channel Bus LVDS Transceiver
General Description
The DS92LV090A is one in a series of Bus LVDS transceiv-
ers designed specifically for the high speed, low power pro-
prietary backplane or cable interfaces. The device operates
from a single 3.3V power supply and includes nine differen-
tial line drivers and nine receivers. To minimize bus loading,
the driver outputs and receiver inputs are internally con-
nected. The separate I/O of the logic side allows for loop
back support. The device also features a flow through pin out
which allows easy PCB routing for short stubs between its
pins and the connector.
The driver translates 3V TTL levels (single-ended) to differ-
ential Bus LVDS (BLVDS) output levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition, the differential signaling provides
common mode noise rejection of ±1V.
The receiver threshold is less than ±100 mV over a ±1V
common mode range and translates the differential Bus
LVDS to standard (TTL/CMOS) levels. (See Applications In-
formation Section for more details.)
Features
n Bus LVDS Signaling
n 3.2 nanosecond propagation delay max
n Chip to Chip skew ±800ps
n Low power CMOS design
n High Signaling Rate Capability (above 100 Mbps)
n 0.1V to 2.3V Common Mode Range for V_ID = 200mV
n ±100 mV Receiver Sensitivity
n Supports open and terminated failsafe on port pins
n 3.3V operation
n Glitch free power up/down (Driver & Receiver disabled)
n Light Bus Loading (5 pF typical) per Bus LVDS load
n Designed for Double Termination Applications
n Balanced Output Impedance
n Product offered in 64 pin TQFP package
n High impedance Bus pins on power off (V_CC = 0V)
n Driver Channel to Channel skew (same device) 230ps
typical
n Receiver Channel to Channel skew (same device)
370ps typical
Simplified Functional Diagram
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