DS92LV010A_07 Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – Bus LVDS 3.3/5.0V Single Transceiver

November 28, 2007
DS92LV010A
Bus LVDS 3.3/5.0V Single Transceiver
General Description
The DS92LV010A is one in a series of transceivers designed
specifically for the high speed, low power proprietary bus
backplane interfaces. The device operates from a single 3.3V
or 5.0V power supply and includes one differential line driver
and one receiver. To minimize bus loading the driver outputs
and receiver inputs are internally connected. The logic inter-
face provides maximum flexibility as 4 separate lines are
provided (DIN, DE, RE, and ROUT). The device also features
flow through which allows easy PCB routing for short stubs
between the bus pins and the connector. The driver has 10
mA drive capability, allowing it to drive heavily loaded back-
planes, with impedance as low as 27 Ohms.
The driver translates between TTL levels (single-ended) to
Low Voltage Differential Signaling levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition the differential signaling provides com-
mon mode noise rejection of ±1V.
The receiver threshold is ±100mV over a ±1V common mode
range and translates the low voltage differential levels to stan-
dard (CMOS/TTL) levels.
Features
■ ^{Bus LVDS Signaling (BLVDS)}
■ ^{Designed for Double Termination Applications}
■ ^{Balanced Output Impedance}
■ ^{Lite Bus Loading 5pF typical}
■ ^{Glitch free power up/down (Driver disabled)}
■ ^{3.3V or 5.0V Operation}
■ ^{±1V Common Mode Range}
■ ^{±100mV Receiver Sensitivity}
■ ^{High Signaling Rate Capability (above 100 Mbps)}
■ ^{Low Power CMOS design}
■ ^{Product offered in 8 lead SOIC package}
■ ^{Industrial Temperature Range Operation}
Connection Diagram
Block Diagram
10005201
Order Number DS92LV010ATM
See NS Package Number M08A
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation 100052
10005202
www.national.com