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DS90C032B Datasheet, PDF (1/9 Pages) National Semiconductor (TI) – LVDS Quad CMOS Differential Line Receiver
March 1999
DS90C032B
LVDS Quad CMOS Differential Line Receiver
General Description
The DS90C032B is a quad CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
The DS90C032B accepts low voltage (350 mV) differential
input signals and translates them to CMOS (TTL compatible)
output levels. The receiver supports a TRI-STATE® function
that may be used to multiplex outputs. The receiver also sup-
ports OPEN and terminated (100Ω) input Fail-safe. Receiver
output will be HIGH for both Fail-safe conditions.
The DS90C032B provides power-off high impedance LVDS
inputs. This feature assures minimal loading effect on the
LVDS bus lines when VCC is not present.
The DS90C032B and companion line driver (DS90C031B)
provide a new alternative to high power pseudo-ECL devices
for high speed point-to-point interface applications.
Features
n >155.5 Mbps (77.7 MHz) switching rates
n Accepts small swing (350 mV) differential signal levels
n High Impedance LVDS inputs with power down
n Ultra low power dissipation
n 600 ps maximum differential skew (5V, 25˚C)
n 6.0 ns maximum propagation delay
n Industrial operating temperature range
n Available in surface mount packaging (SOIC)
n Pin compatible with DS26C32A, MB570 (PECL) and
41LF (PECL)
n Supports OPEN and terminated input fail-safe
n Conforms to ANSI/TIA/EIA-644 LVDS standard
Connection Diagram
Dual-In-Line
Functional Diagram
DS100990-1
Order Number
DS90C032BTM
See NS Package
Number M16A
Receiver Truth Table
ENABLES
EN
EN*
L
H
All other combinations
of ENABLE inputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100990
DS100990-2
INPUTS
RIN+ − RIN−
X
VID ≥ 0.1V
VID ≤ −0.1V
Fail-safe OPEN
or Terminated
OUTPUT
ROUT
Z
H
L
H
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