DS7836 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – Quad NOR Unified Bus Receiver

February 1996
DS7836 DS8836 Quad NOR Unified Bus Receiver
General Description
The DS7836 DS8836 are quad 2-input receivers designed
for use in bus organized data transmission systems inter-
connected by terminated 120X impedance lines The exter-
nal termination is intended to be 180X resistor from the bus
to the a5V logic supply together with a 390X resistor from
the bus to ground The design employs a built-in input hys-
teresis providing substantial noise immunity Low input cur-
rent allows up to 27 driver receiver pairs to utilize a com-
mon bus Performance is optimized for systems with bus
rise and fall times ^s 1 0 ms V
Features
Y _{Low input current with normal VCC or VCC} e _0V
(15 mA typ)
Y _{Built-in input hysteresis (1V typ)}
Y _{High noise immunity (2V typ)}
Y _{Temperature-insensitive input thresholds track bus logic}
levels
Y _{TTL compatible output}
Y _{Matched optimized noise immunity for ‘‘1’’ and ‘‘0’’}
levels
Y _{High speed (18 ns typ)}
Typical Application
120X Unified Data Bus
Connection Diagram
Dual-In-Line Package
TL F 5810 – 1
Top View
Order Number DS7836J or DS8836N
See NS Package Number J14A or N14A
TL F 5810 – 2
C1996 National Semiconductor Corporation TL F 5810
RRD-B30M36 Printed in U S A
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