DS36C279_00 Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – Low Power EIA-RAS-485 Transceiver with Sleep Mode

July 2000
DS36C279
Low Power EIA-RS-485 Transceiver with Sleep Mode
General Description
The DS36C279 is a low power differential bus/line trans-
ceiver designed to meet the requirements of RS-485 Stan-
dard for multipoint data transmission. In addition it is com-
patible with TIA/EIA-422-B.
The sleep mode feature automatically puts the device in a
power saving mode when both the driver and receiver are
disabled.†† The device is ideal for use in power conscious
applications where the device may be disabled for extended
periods of time.
The driver and receiver outputs feature TRI-STATE^® capa-
bility. The driver outputs operate over the entire common
mode range of −7V to +12V. Bus contention or fault situa-
tions that cause excessive power dissipation within the de-
vice are handled by a thermal shutdown circuit, which forces
the driver outputs into a high impedance state.
The receiver incorporates a fail safe circuit which guarantees
a high output state when the inputs are left open.†
The DS36C279T is fully specified over the industrial tem-
perature range (−40˚C to +85˚C).
Features
n 100% RS-485 compliant
— Guaranteed RS-485 device interoperation
n Low power CMOS design: I_CC 500 µA max
n Automatic sensing sleep mode
— Reduces I_CC to 10 µA maximum
n Built-in power up/down glitch-free circuitry
— Permits live transceiver intersection/displacement
n SOIC packages
n Industrial temperature range: −40˚C to +85˚C
n On-board thermal shutdown circuitry
— Prevents damage to the device in the event of
excessive power dissipation
n Wide common mode range: −7V to +12V
n Receive open input fail-safe (Note 1)
n ¹â„4 unit load (DS36C279): ≥ 128 nodes
n ¹â„2 unit load (DS36C279T): ≥ 64 nodes
n ESD (Human Body Model): ≥ 2 kV
n Drop-in replacement for:
— LTC485 MAX485 DS75176 DS3695
Connection and Logic Diagram
01205301
Order Number DS36C279M, DS36C279TM
See NS Package Number M08A
Truth Table
DRIVER SECTION
RE*
DE
DI
DO/RI
X
H
H
H
X
H
L
L
X
L
X
Z
RECEIVER SECTION
RE*
DE
RI-RI*
L
L
≥+0.2V
L
L
≤−0.2V
H
L
X
L
L
OPEN (Note 1)
DO*/RI*
L
H
Z
RO
H
L
Z (Note 2)
H
Note 1: Non-terminated, open input only
Note 2: Device enters sleep mode if enable conditions are held > 600 ns
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation DS012053
www.national.com