DS34C86T Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Quad CMOS Differential Line Receiver

May 1998
DS34C86T
Quad CMOS Differential Line Receiver
General Description
The DS34C86T is a quad differential line receiver designed
to meet the RS-422, RS-423, and Federal Standards 1020
and 1030 for balanced and unbalanced digital data transmis-
sion, while retaining the low power characteristics of CMOS.
The DS34C86T has an input sensitivity of 200 mV over the
common mode input voltage range of ±7V. Hysteresis is pro-
vided to improve noise margin and discourage output insta-
bility for slowly changing input waveforms.
The DS34C86T features internal pull-up and pull-down resis-
tors which prevent output oscillation on unused channels.
Separate enable pins allow independent control of receiver
pairs. The TRI-STATE^® outputs have 6 mA source and sink
capability. The DS34C86T is pin compatible with the
DS3486.
Features
n CMOS design for low power
n ±0.2V sensitivity over the input common mode voltage
range
n Typical propagation delays: 19 ns
n Typical input hysteresis: 60 mV
n Inputs won’t load line when V_CC = 0V
n Meets the requirements of EIA standard RS-422
n TRI-STATE outputs for system bus compatibility
n Available in surface mount
n Open input Failsafe feature, output high for open input
Logic Diagram
Connection Diagram
Dual-In-Line Package
Truth Table
DS008699-1
Enable
L
H
H
H
*Open, not terminated
Z = TRI-STATE
Input
X
V_ID ≥ V_TH (Max)
V_ID ≤ V_TH (Min)
Open*
Output
Z
H
L
H
DS008699-2
Top View
Order Number DS34C86TM, and DS34C86TN
See NS Package Number M16A and N16E
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS008699
www.national.com