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DS32EL0421_09 Datasheet, PDF (1/28 Pages) National Semiconductor (TI) – 125-312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface | |||
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DS32EL0421, DS32ELX0421
June 2, 2009
125 â 312.5 MHz FPGA-Link Serializer with DDR LVDS
Parallel Interface
General Description
The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz
(DDR) serializer for high-speed serial transmission over FR-4
printed circuit board backplanes, balanced cables, and optical
fiber. This easy-to-use chipset integrates advanced signal
and clock conditioning functions, with an FPGA friendly inter-
face.
The DS32EL0421/DS32ELX0421 serializes up to 5 parallel
input LVDS channels to create a maximum data payload of
3.125 Gbps. If the integrated DC-balance encoding is en-
abled, the maximum data payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature remote
sense capability to automatically detect and negotiate link
status with its companion DS32EL0124/DS32ELX0124 de-
serializers without requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins, board
trace count and alleviates EMI issues, when compared to tra-
ditional single-ended wide bus interfaces.
The DS32EL0421/DS32ELX0421 is programmable through
a SMBus interface as well as through control pins.
Target Applications
â Imaging: Industrial, Medical Security, Printers
â Displays: LED walls, Commercial
â Video Transport
â Communication Systems
â Test and Measurement
â Industrial Bus
Features
â 5-bit DDR LVDS parallel data interface
â Programmable transmit de-emphasis
â Configurable output levels (VOD)
â Selectable DC-balanced encoder
â Selectable data scrambler
â Remote Sense for automatic detection and negotiation of
link status
â On chip LC VCOs
â Redundant serial output (ELX device only)
â Data valid signaling to assist with synchronization of
multiple receivers
â Supports AC- and DC-coupled signaling
â Integrated CML and LVDS terminations
â Configurable PLL loop bandwidth
â Programmable output termination (50⦠or 75â¦).
â Built-in test pattern generator
â Loss of lock and error reporting
â Configurable via SMBus
â 48-pin LLP package with exposed DAP
Key Specifications
â 1.25 to 3.125 Gbps serial data rate
â 125 to 312.5 MHz DDR parallel clock
â -40° to +85°C temperature range
â >8 kV ESD (HBM) protection
â Low Intrinsic Jitter â 35ps at 3.125 Gbps
Typical Application
© 2009 National Semiconductor Corporation 300321
30032101
www.national.com
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