DS25CP104A Datasheet, PDF (1/28 Pages) National Semiconductor (TI) – 3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit Pre-Emphasis and Receive Equalization

DS25CP104A / DS25CP114
May 13, 2009
3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit
Pre-Emphasis and Receive Equalization
General Description
The DS25CP104A and DS25CP114 are 3.125 Gbps 4x4
LVDS crosspoint switches optimized for high-speed signal
routing and switching over lossy FR-4 printed circuit board
backplanes and balanced cables. Fully differential signal
paths ensure exceptional signal integrity and noise immunity.
The non-blocking architecture allows connections of any input
to any output or outputs. The switch configuration can be ac-
complished via external pins or the System Management Bus
(SMBus) interface.
The DS25CP104A and DS25CP114 feature four levels (Off,
Low, Medium, High) of transmit pre-emphasis (PE) and four
levels (Off, Low, Medium, High) of receive equalization (EQ)
settable via the SMBus interface. Off and Medium PE levels
and Off and Low EQ levels are settable with the external pins.
In addition, the SMBus circuitry enables the loss of signal
(LOS) monitors that can inform a system of the presence of
an open inputs condition (e.g. disconnected cable).
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. On the DS25CP104A each differential input and
output is internally terminated with a 100Ω resistor to lower
return losses, reduce component count and further minimize
board space. For added design flexibility the 100Ω input ter-
minations on the DS25CP114 have been eliminated. This
enables a designer to build custom crosspoint configurations
and distribution circuits that require a limited multidrop sig-
naling topology.
Features
■ ^{DC - 3.125 Gbps low jitter, low skew, low power operation}
■ ^{Pin and SMBus configurable, fully differential, non-}
blocking architecture
■ ^{Pin (two levels) and SMBus (four levels) selectable pre-}
emphasis and equalization eliminate ISI jitter
■ ^{Wide Input Common Mode Range enables easy interface}
to CML and LVPECL drivers
■ ^{LOS circuitry detects open inputs fault condition}
■ ^{On-chip 100Ω input and output termination minimizes}
insertion and return losses, reduces component count and
minimizes board space. The DS25CP114 eliminates the
on-chip input termination for added design flexibility.
■ ^{8 kV ESD on LVDS I/O pins protects adjoining}
components
■ ^{Small 6 mm x 6 mm LLP-40 space saving package}
Applications
■ ^{SD/HD/3G HD SDI Routers}
■ ^{OC-48 / STM-16}
■ ^{InfiniBand and FireWire}
Typical Application
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