DS25BR110_0711 Datasheet, PDF (1/16 Pages) National Semiconductor (TI) – 3.125 Gbps LVDS Buffer with Receive Equalization

November 6, 2007
DS25BR110
3.125 Gbps LVDS Buffer with Receive Equalization
General Description
The DS25BR110 is a single channel 3.125 Gbps LVDS buffer
optimized for high-speed signal transmission over lossy FR-4
printed circuit board backplanes and balanced metallic ca-
bles. A fully differential signal path ensures exceptional signal
integrity and noise immunity.
The DS25BR110 features four levels of receive equalization
(EQ), making it ideal for use as a receiver device. Other LVDS
devices with similar IO characteristics include the following
products. The DS25BR120 features four levels of pre-em-
phasis for use as an optimized driver device, while the
DS25BR100 features both pre-emphasis and equalization for
use as an optimized repeater device. The DS25BR150 is a
buffer/repeater with the lowest power consumption and does
not feature transmit pre-emphasis nor receive equalization.
Wide input common mode range allows the receiver to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires minimal
space on the board while the flow-through pinout allows easy
board layout. The differential inputs and outputs are internally
terminated with a 100Ω resistor to lower device input and out-
put return losses, reduce component count, and further min-
imize board space.
Features
■ ^{DC - 3.125 Gbps low jitter, high noise immunity, low power}
operation
■ ^{Four levels of receive equalization reduce ISI jitter}
■ ^{On-chip 100Ω input and output termination minimizes}
insertion and return losses, reduces component count and
minimizes board space
■ ^{7 kV ESD on LVDS I/O pins protects adjoining}
components
■ ^{Small 3 mm x 3 mm 8-LLP space saving package}
Applications
■ ^{Clock and data buffering}
■ ^{Metallic cable equalization}
■ ^{FR-4 equalization}
Typical Application
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