DP8496 Datasheet, PDF (1/92 Pages) National Semiconductor (TI) – SCSI-2 Disk Data Controller

PRELIMINARY
December 1991
DP8496 DP8497
SCSI-2 Disk Data Controller
General Description
The DP8496 7 is a highly integrated high-performance
CMOS SCSI disk data controller It is designed for use in-
side intelligent hard disk drives that utilize the Small Com-
puter System Interface (SCSI) standard It can also be used
in ESDI SMD and ST506 bridging controller applications
The DP8496 7 includes most of the data path functions
needed to implement a complete hard disk controller It in-
cludes a full featured SCSI Bus Controller Buffer Memory
Interface with pipelined pointers fast Disk Data Controller
and a Processor Interface
With the addition of National Semiconductor read-channel
chips such as a PLL Synchronizer and Encoder Decoder a
pulse detector and a head amplifier complete data-path
electronics of a SCSI drive can be implemented A micro-
controller such as National’s HPC^TM may be used to man-
age the SCSI commands and the drive specific control sig-
nals The high level of intelligence implemented on the
DP8496 7 means lower overhead for the disk-drive’s em-
bedded microcontroller making possible a high-perform-
ance design employing only one micro-controller
The DP8496 provides on-chip single-ended transceivers for
driving the SCSI bus The DP8497 provides all control sig-
nals necessary for direct interfacing with differential trans-
ceivers recommended for Fast SCSI option of SCSI-2
Features
Y _{High disk data rates}
DP8496 7-33 33 Mbit sec
DP8496 7-50 50 Mbit sec
Y _{Synchronous SCSI-2 transfer rates up to 10 MByte sec}
with offset up to 16 (Fast option)
Y _{Asynchronous SCSI transfer rates up to 5 MByte sec}
Y _{Support for Fast Page Mode and Static Column De-}
code type DRAMs
Y _{Attains sustained buffer bandwidths above 9 MByte sec}
with byte-wide memory configuration
Y _{Word-wide buffer memory port allows sustained band-}
widths of 17 MByte sec
Y _{Buffer memory up to 4 MBytes DRAM or 1 MByte}
SRAM
Y _{On-chip DMA with buffered pointer addresses}
Y _{Multi-phase type SCSI commands}
Y _{Parity error checking on SCSI buffer memory and all}
internal data paths
Y _{Programmable format and sectoring modes including}
soft pseudo-hard and hard
Y _{32 48 or 56-bit computer generated ECC with on-chip}
correction
Y _{On-chip single-ended transceivers on DP8496 DP8497}
interfaces directly with differential transceivers for Fast
SCSI
Y _{Available in 100-pin PQFP package}
System Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
HPCTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11212
TL F 11212 – 1
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