DP8483 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – TTL to 100k ECL Level Translator with Latch

April 1990
DP8483 TTL to 100k ECL Level Translator with Latch
General Description
This circuit translates TTL input levels to ECL output levels
and provides a fall-through latch The outputs are gated with
CS providing for wire ORing of outputs The strobe and chip
select inputs operate at ECL levels
Features
Y _{16-pin DIP or S O}
Y _{ECL control inputs}
Y _{CS provided for wire ORing of output bus}
Y _{100k ECL I O compatible}
Y _{3 0 ns typical propagation delay}
Logic and Connection Diagram
Truth Table
Dual-In-Line Package
D Q STR CS
HL
L
H
LH
L
H
XQ
H
H
XL
X
L
Hehigh level (most positive)
Lelow level (most negative)
Xedon’t care
Order Number DP8483J
DP8483M or DP8483N
See NS Package Number J16A M16B or N16A
Top View
TL F 5864 – 1
C1995 National Semiconductor Corporation TL F 5864
RRD-B30M105 Printed in U S A