DP8482A Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – 100k ECL to TTL Level Translator with Latch

April 1990
DP8482A 100k ECL to TTL Level Translator with Latch
General Description
This circuit translates ECL input levels to TTL output levels
and provides a fall-through latch The TRI-STATE outputs
are designed to drive standard 50 pF loads The strobe and
chip select inputs operate at ECL levels
Features
Y _{16-pin DIP or S O}
Y _{TRI-STATE outputs}
Y _{ECL control inputs}
Y _{8 ns typical propagation delay with 50 pF load}
Y _{Outputs are TRI-STATE during power up down for}
glitch free operation
Y _{100k ECL input compatible}
Logic and Connection Diagram
Dual-In-Line Package
Truth Table
D
Q
STR CS
H
L
L
L
L
H
L
L
X
Q
H
L
X Hi-Z
X
H
Hehigh level (most positive)
Lelow level (most negative)
Xedon’t care
Order Number DP8482AJ DP8482AM or DP8482AN
See NS Package Number J16A N16A or M16B
Top View
TL F 5863 – 1
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL F 5863
RRD-B30M115 Printed in U S A