DP8481 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – TTL to 10k ECL Level Translator with Latch

June 1986
DP8481 TTL to 10k ECL Level Translator with Latch
General Description
This circuit translates TTL input levels to ECL output levels
and provides a fall-through latch The outputs are gated with
CS providing for wire ORing of outputs The strobe and chip
select inputs operate at ECL levels
Logic and Connection Diagram
Features
Y _{16-pin flat-pack or DIP}
Y _{ECL control inputs}
Y _{CS provided for wire ORing of output bus}
Y _{10k ECL I O compatible}
Y _{3 0 ns typical propagation delay}
Truth Table
Dual-In-Line Package
D Q STR CS
HL
L
H
LH
L
H
XQ
H
H
XL
X
L
Hehigh level (most positive)
Lelow level (most negative)
Xedon’t care
Order Number
DP8481F DP8481J or DP8481N
See NS Package
F16B J16A or N16A
Top View
TL F 5862 – 1
C1995 National Semiconductor Corporation TL F 5862
RRD-B30M115 Printed in U S A