DP8480A Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – DP8480A 10k ECL to TTL Level Translator with Latch

April 1990
DP8480A 10k ECL to TTL Level Translator with Latch
General Description
This circuit translates ECL input levels to TTL output levels
and provides a fall-through latch The TRI-STATE outputs
are designed to drive standard 50 pF loads The strobe and
chip select inputs operate at ECL levels
Features
Y _{16-pin DIP}
Y _{TRI-STATE outputs}
Y _{ECL control inputs}
Y _{8 ns typical propagation delay with 50 pF load}
Y _{Outputs are TRI-STATE during power up down for}
glitch free operation
Y _{10k ECL input compatible}
Logic and Connection Diagram
Truth Table
Dual-In-Line Package
D
Q
STR
CS
H
L
L
L
L
H
L
L
X
Q
H
L
X
Hi-Z
X
H
H e high level (most positive)
L e low level (most negative)
X e don’t care
Order Number DP8480AJ or DP8480AN
See NS Package Number J16A or N16A
Top View
TL F 5861 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 5861
RRD-B30M105 Printed in U S A