DP8428 Datasheet, PDF (1/26 Pages) National Semiconductor (TI) – 1 Megabit High Speed Dynamic RAM Controller/Drivers

September 1991
DP8428 NS32828 DP8429 NS32829
1 Megabit High Speed Dynamic RAM Controller Drivers
General Description
The DP8428 and DP8429 1M DRAM Controller Drivers are
designed to provide ‘‘No-Waitstate’’ CPU interface to Dy-
namic RAM arrays of up to 8 Mbytes and larger The
DP8428 and DP8429 are tailored for 32-bit and 16-bit sys-
tem requirements respectively Both devices are fabricated
using National’s new oxide isolated Advanced Low power
Schottky (ALS) process and use design techniques which
enable them to significantly out-perform all other LSI or dis-
crete alternatives in speed level of integration and power
consumption
Each device integrates the following critical 1M DRAM con-
troller functions on a single monolithic device ultra precise
delay line 9 bit refresh counter fall-through row column
and bank select input latches Row Column address mux-
ing logic on-board high capacitive-load RAS CAS Write
Enable and Address output drivers and precise control sig-
nal timing for all the above
In order to specify each device for ‘‘true’’ worst case operat-
ing conditions all timing parameters are guaranteed while
the chip is driving the capacitive load of 88 DRAMs includ-
ing trace capacitance The chip’s delay timing logic makes
use of a patented new delay line technique which keeps AC
skew to g3 ns over the full V_CC range of g10% and tem-
perature range of b55 C to a125 C The DP8428 and
DP8429 guarantee a maximum RASIN to CASOUT delay of
80 ns or 70 ns even while driving an 8 Mbyte memory array
with error correction check bits included Two speed select-
ed options of these devices are shown in the switching
characteristics section of this document
(Continued)
Features
Y _{Makes DRAM interface and refresh tasks appear virtu-}
ally transparent to the CPU making DRAMs as easy to
use as static RAMs
Y _{Specifically designed to eliminate CPU wait states up to}
10 MHz or beyond
Y _{Eliminates 20 discrete components for significant board}
real estate reduction system power savings and the
elimination of chip-to-chip AC skewing
Y _{On-board ultra precise delay line}
Y _{On-board high capacitive RAS CAS WE and Address}
drivers (specified driving 88 DRAMs directly)
Y _{AC specified for directly addressing up to 8 Mbytes}
Y _{Low power high speed bipolar oxide isolated process}
Y _{Downward pin and function compatible with 256k}
DRAM Controller Drivers DP8409A DP8417 DP8418
and DP8419
Contents
Y _{System and Device Block Diagrams}
Y _{Recommended Companion Components}
Y _{Device Connection Diagrams and Pin Definitions}
Y _{Device Differences DP8428 vs DP8429}
Y _{Mode of Operation}
(Descriptions and Timing Diagrams)
Y _{Application Description and Diagrams}
Y _{DC AC Electrical Specifications Timing Diagrams and}
Test Conditions
System Diagram
TRI-STATE is a registered trademark of National Semiconductor Corp
PAL is a registered trademark of and used under license with Monolithic Memories Inc
C1995 National Semiconductor Corporation TL F 8649
TL F 8649 – 1
RRD-B30M105 Printed in U S A