DP8420A Datasheet, PDF (1/58 Pages) National Semiconductor (TI) – microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

July 1992
DP8420A 21A 22A microCMOS Programmable
256k 1M 4M Dynamic RAM Controller Drivers
General Description
The DP8420A 21A 22A dynamic RAM controllers provide a
low cost single chip interface between dynamic RAM and
all 8- 16- and 32-bit systems The DP8420A 21A 22A gen-
erate all the required access control signal timing for
DRAMs An on-chip refresh request clock is used to auto-
matically refresh the DRAM array Refreshes and accesses
are arbitrated on chip If necessary a WAIT or DTACK out-
put inserts wait states into system access cycles including
burst mode accesses RAS low time during refreshes and
RAS precharge time after refreshes and back to back ac-
cesses are guaranteed through the insertion of wait states
Separate on-chip precharge counters for each RAS output
can be used for memory interleaving to avoid delayed back
to back accesses because of precharge An additional fea-
ture of the DP8422A is two access ports to simplify dual
accessing Arbitration among these ports and refresh is
done on chip
Features
Y _{On chip high precision delay line to guarantee critical}
DRAM access timing parameters
Y _{microCMOS process for low power}
Y _{High capacitance drivers for RAS CAS WE and DRAM}
address on chip
Y _{On chip support for nibble page and static column}
DRAMs
Y _{Byte enable signals on chip allow byte writing in a word}
size up to 32 bits with no external logic
Y _{Selection of controller speeds 20 MHz and 25 MHz}
Y _{On board Port A Port B (DP8422A only) refresh arbitra-}
tion logic
Y _{Direct interface to all major microprocessors (applica-}
tion notes available)
Y _{4 RAS and 4 CAS drivers (the RAS and CAS configura-}
tion is programmable)
Control
DP8420A
DP8421A
DP8422A
of Pins
(PLCC)
68
68
84
of Address
Outputs
9
10
11
Largest
DRAM
Possible
256 kbit
1 Mbit
4 Mbit
Direct Drive
Memory
Capacity
4 Mbytes
16 Mbytes
64 Mbytes
Access
Ports
Available
Single Access Port
Single Access Port
Dual Access Ports (A and B)
Block Diagram
DP8420A 21A 22A DRAM Controller
TRI-STATE is a registered trademark of National Semiconductor Corporation
Staggered RefreshTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 8588
FIGURE 1
TL F 8588 – 5
RRD-B30M105 Printed in U S A