DP83950B Datasheet, PDF (1/80 Pages) National Semiconductor (TI) – RIC™ Repeater Interface Controller

October 1995
DP83950B RIC^TM
Repeater Interface Controller
General Description
The DP83950B Repeater Interface Controller ‘‘RIC’’ may be
used to implement an IEEE 802 3 multiport repeater unit It
fully satisfies the IEEE 802 3 repeater specification including
the functions defined by the repeater segment partition and
jabber lockup protection state machines
The RIC has an on-chip phase-locked-loop (PLL) for Man-
chester data decoding a Manchester encoder and an Elas-
ticity Buffer for preamble regeneration
Each RIC can connect to 13 cable segments via its network
interface ports One port is fully AUI compatible and is able
to connect to an external MAU using the maximum length of
AUI cable The other 12 ports have integrated 10BASE-T
transceivers These transceiver functions may be bypassed
so that the RIC may be used with external transceivers for
example DP8392 coaxial transceivers In addition large re-
peater units containing several hundred ports may be con-
structed by cascading RICs together over an Inter-RIC bus
The RIC is configurable for specific applications It provides
port status information for LED array displays and a simple
interface for system processors The RIC posseses multi-
function counter and status flag arrays to facilitate network
statistics gathering A serial interface known as the Man-
agement Interface is available for the collection of data in
Managed Hub applications
Features
Y _{Compliant with the IEEE 802 3 Repeater Specification}
Y _{13 network connections (ports) per chip}
Y _{Selectable on-chip twisted-pair transceivers}
Y _{Cascadable for large hub applications}
Y _{Compatible with AUI compliant transceivers}
Y _{On-chip Elasticity Buffer Manchester encoder and de-}
coder
Y _{Separate partition state machines for each port}
Y _{Provides port status information for LED displays in-}
cluding receive collision partition and link status
Y _{Power-up configuration options}
Repeater and Partition Specifications Transceiver Inter-
face Status Display Processor Operations
Y _{Simple processor interface for repeater management}
and port disable
Y _{On-chip Event Counters and Event Flag Arrays}
Y _{Serial Management Interface to combine packet and}
repeater status information together
Y _{CMOS process for low power dissipation}
Y _{Single 5V supply}
Table of Contents
1 0 SYSTEM DIAGRAM
2 0 CONNECTION DIAGRAM
3 0 PIN DESCRIPTIONS
4 0 BLOCK DIAGRAM
5 0 FUNCTIONAL DESCRIPTION
6 0 HUB MANAGEMENT SUPPORT
7 0 PORT LOGIC FUNCTIONS
8 0 RIC REGISTER DESCRIPTIONS
9 0 AC AND DC SPECIFICATIONS
10 0 AC TIMING TEST CONDITIONS
11 0 PHYSICAL DIMENSIONS
1 0 System Diagram
Simple RIC Hub
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C1995 National Semiconductor Corporation TL F 11096
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