DP83848I Datasheet, PDF (1/82 Pages) National Semiconductor (TI) – Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

September 2005
DP83848I PHYTER^® - Industrial Temperature
Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
General Description
Features
The DP83848I is a robust fully featured 10/100 single
port Physical Layer device offering low power con-
sumption, including several intelligent power down
states. These low power modes increase overall prod-
uct reliability due to decreased power dissipation. Sup-
porting multiple intelligent power modes allows the
application to use the absolute minimum amount of
power needed for operation. In addition to low power,
the DP83848I is optimized for cable length perfor-
mance far exceeding IEEE specifications.
• Low-power 3.3V, 0.18µm CMOS technology
• Low power consumption < 270mW Typical
• 3.3V MAC Interface
• Auto-MDIX for 10/100 Mb/s
• Energy Detection Mode
• 25 MHz clock out
• SNI Interface (configurable)
• RMII Rev. 1.2 Interface (configurable)
The DP83848I includes a 25MHz clock out. This
means that the application can be designed with a
minimum of external parts, which in turn results in the
lowest possible total cost of the solution.
The DP83848I easily interfaces to twisted pair media
via an external transformer and fully supports JTAG
IEEE specification 1149.1 for ease of manufacturing.
Additionally both MII and RMII are supported ensuring
ease and flexibility of design.
The DP83848I features integrated sublayers to sup-
port both 10BASE-T and 100BASE-TX Ethernet proto-
cols, which ensures compatibility and interoperability
with all other standards based Ethernet solutions.
The DP83848I is offered in a small form factor (48 pin
LQFP) so that a minimum of board space is needed.
• MII Serial Management Interface (MDC and MDIO)
• IEEE 802.3u MII
• IEEE 802.3u Auto-Negotiation and Parallel Detection
• IEEE 802.3u ENDEC, 10BASE-T transceivers and filters
• IEEE 802.3u PCS, 100BASE-TX transceivers and filters
• IEEE 1149.1 JTAG
• Integrated ANSI X3.263 compliant TP-PMD physical sub-
layer with adaptive equalization and Baseline Wander com-
pensation
• Programmable LED support Link, 10 /100 Mb/s Mode, Activ-
ity, and Collision Detect
• Single register access for complete PHY status
• 10/100 Mb/s packet BIST (Built in Self Test)
• 48-pin LQFP package (7mm) x (7mm)
Applications
• High End Peripheral Devices
• Industrial Controls and Factory Automation
• General Embedded Applications
System Diagram
MPU/CPU
MII/RMII/SNI
DP83848I
10/100 Mb/s
25 MHz
Clock
Source
Status
LEDs
Typical Application
®
PHYTER is a registered trademark of National Semiconductor.
© 2005 National Semiconductor Corporation
1
10BASE-T
or
100BASE-TX
www.national.com