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DP83266 Datasheet, PDF (1/152 Pages) National Semiconductor (TI) – MACSITM Device (FDDI Media Access Controller and System Interface) | |||
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PRELIMINARY
October 1994
DP83266 MACSITM Device
(FDDI Media Access Controller and System Interface)
General Description
The DP83266 Media Access Controller and System Inter-
face (MACSI) implements the ANSI X3T9 5 Standard Media
Access Control (MAC) protocol for operation in an FDDI
token ring and provides a comprehensive System Interface
The MACSI device transmits receives repeats and strips
tokens and frames It produces and consumes optimized
data structures for efficient data transfer Full duplex archi-
tecture with through parity allows diagnostic transmission
and self testing for error isolation and point-to-point connec-
tions
The MACSI device includes the functionality of both the
DP83261 BMACTM device and the DP83265 BSI-2TM device
with additional enhancements for higher performance and
reliability
Features
Y Over 9 kBytes of on-chip FIFO
Y 5 DMA channels (2 Output and 3 Input)
Y 12 5 MHz to 25 MHz operation
Y Full duplex operation with through parity
Y Supports JTAG boundary scan
Y Real-time Void stripping indicator for bridges
Y On-chip address bit swapping capability
Y 32-bit wide Address Data path with byte parity
Y Programmable transfer burst sizes of 4 or 8
32-bit words
Y Receive frame filtering services
Y Frame-per-Page mode controllable on each
DMA channel
Y Demultiplexed Addresses supported on ABus
Y New multicast address matching feature
Y ANSI X3T9 5 MAC standard defined ring
service options
Y Supports all FDDI Ring Scheduling Classes
(Synchronous Asynchronous etc )
Y Supports Individual Group Short Long and
External Addressing
Y Generates Beacon Claim and Void frames
Y Extensive ring and station statistics gathering
Y Extensions for MAC level bridging
Y Enhanced SBus compatibility
Y Interfaces to DRAMs or directly to system bus
Y Supports frame Header Info splitting
Y Programmable Big or Little Endian alignment
Block Diagram
TL F 11705 â 1
FIGURE 1-1 FDDI Chip Set Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
BMACTM BSI-2TM MACSITM and PLAYERaTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11705
RRD-B30M105 Printed in U S A
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