DP83222 Datasheet, PDF (1/12 Pages) National Semiconductor (TI) – CYCLONE Twisted Pair FDDI Stream Cipher Device

August 1994
DP83222
CYCLONE^TM Twisted Pair FDDI Stream Cipher Device
General Description
The DP83222 CYCLONE Stream Cipher Scrambler
Descrambler Device is an integrated circuit designed to in-
terface directly with the serial bit streams of a Twisted Pair
FDDI PMD The DP83222 is designed to be fully compatible
with the National Semiconductor FDDI Chip Sets including
the DP83223 TWISTER^TM (Twisted Pair Transceiver) The
DP83222 requires a 125 MHz Transmit Clock and corre-
sponding Receive Clock for synchronous data scrambling
and descrambling The DP83222 is compliant with the ANSI
X3T9 5 TP-PMD draft standard and is required for the re-
duction of EMI emission over unshielded media The
DP83222 is specified to work in conjunction with existing
twisted pair transceiver signalling schemes such as MLT-3
or NRZI and enables high bandwidth transmission over
Twisted Pair copper media
Features
Y _{Enables 100 Mbps FDDI signalling over Category 5}
Unshielded Twisted Pair (UTP) cable and Type 1
Shielded Twisted Pair (STP)
Y _{Reduces EMI emissions over Twisted Pair media}
Y _{Compatible with ANSI X3T9 5 TP-PMD Standard}
Y _{Requires a single} a_{5V supply}
Y _{Transparent mode of operation}
Y _{Flexible NRZ and NRZI format options}
Y _{Advanced BiCMOS process}
Y _{Signal Detect and Clock Detect inputs provided for en-}
hanced functionality
Y _{Suitable for Fiber Optic PMD replacement applications}
Block Diagram
FIGURE 1 DP83222 Block Diagram
TL F 11885 – 1
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C1995 National Semiconductor Corporation TL F 11885
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