DM74LS952 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Dual Rank 8-Bit TRI-STATE®Shift Register

August 1991
DM74LS952 (DM86LS52)
Dual Rank 8-Bit TRI-STATE Shift Register
General Description
These circuits are TRI-STATE edge-triggered 8-bit I O reg-
isters in parallel with 8-bit serial shift registers which are
capable of operating in any of the following modes parallel
load from I O pins to register ‘‘A’’ parallel transfer down
from register ‘‘A’’ to serial shift register ‘‘B’’ parallel transfer
up from shift register ‘‘B’’ to register ‘‘A’’ serial shift of regis-
ter ‘‘B’’ synchronously clear Since the registers are edge-
triggered by the positive transition of the clock the control
lines which determine the mode or operation are completely
independent of the logic level applied to the clock De-
signed for bus-oriented systems these circuits have their
TRI-STATE inputs and outputs on the same pins
Features
Y _{Registers are edge-triggered by the positive transition}
of the clock
Y _{All inputs are PNP transistors}
Y _{Input disable dominates over output disable}
Y _{Output high impedance state does not impede any oth-}
er mode of operation
Y _{8-bit I O pins are TRI-STATE buffers}
Y _{Typical shift frequency is 36 MHz}
Y _{Typical power dissipation is 305 mW}
Y _{All control inputs are active when in an ‘‘L’’ logic state}
Y _{Devices can be cascaded into N-bit word}
Connection Diagram
Dual-In-Line Package
Pin Description
DIS_O Output disable
I_S Serial input
DIS_I Input disable
DIS_TU Transfer up disable
DIS_TD Transfer down disable
DIS_S Shift disable
O_S Serial output
CLK Clock
GND Ground
I O 1 I O 8 8-bit I O pins
V_CC Supply Voltage
Top View
Order Number DM74LS952N or DM86LS52N
See NS Package Number N18A
TL F 6437 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 6437
RRD-B30M105 Printed in U S A