DM74LS461 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – Octal Counter

July 1989
DM54LS461 DM74LS461 Octal Counter
General Description
The LS461 is an 8-bit synchronous counter with parallel
load clear and hold capability Two function select inputs
(I₀ I₁) provide one of four operations which occur synchro-
nously on the rising edge of the clock (CK)
The LOAD operation loads the inputs (D₇ – D₀) into the out-
put register (Q₇ – Q₀) The CLEAR operation resets the out-
put register to all LOWs The HOLD operation holds the
previous value regardless of clock transitions The INCRE-
MENT operation adds one to the output register when the
carry-in input is TRUE (CI e LOW) otherwise the operation
is a HOLD The carry-out (CO) is TRUE (CO e LOW) when
the output register (Q₇ – Q₀) is all HIGHs otherwise FALSE
(CO e HIGH)
The output register (Q₇ – Q₀) is enabled when OE is LOW
and disabled (HI-Z) when OE is HIGH The output drivers
will sink the 24 mA required for many bus interface stand-
ards
Connection Diagram
Two or more LS461 octal counters may be cascaded to
provide larger counters The operation codes were chosen
such that when I₁ is HIGH I₀ may be used to select be-
tween LOAD and INCREMENT as in a program counter
(JUMP INCREMENT)
Features Benefits
Y _{Octal counter for microprogram-counter DMA controller}
and general purpose counting applications
Y _{8 bits match byte boundaries}
Y _{Bus-structured pinout}
Y _{24-pin Skinny Dip saves space}
Y _{TRI-STATE outputs drive bus lines}
Y _{Low current PNP inputs reduce loading}
Y _{Expandable in 8-bit increments}
Standard Test Load
Top View
TL L 8334 – 2
TL L 8334 – 1
Order Number DM54LS461J
DM74LS461J or DM74LS461N
See NS Package Number J24F or N24C
Function Table
OE CK I1 I0 CI D7 – D0 Q7 – Q0 Operation
H X XXX X
Z
HI-Z
L uLLX X
L
CLEAR
L uLHX X
Q
HOLD
L uHL X D
D
LOAD
L uHHH X
Q
HOLD
L uHH L
X
Q plus 1 INCREMENT
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL L 8334
RRD-B30M115 Printed in U S A