DM74LS197 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Presettable Binary Counters

February 1992
DM74LS197 Presettable Binary Counters
General Description
The ’LS197 ripple counter contains divide-by-two and di-
vide-by-eight sections which can be combined to form a
modulo-16 binary counter State changes are initiated by
the falling edge of the clock The ’LS197 has a Master Re-
set (MR) input which overrides all other inputs and asyn-
chronously forces all outputs LOW A Parallel Load input
(PL) overrides clocked operations and asynchronously
loads the data on the Parallel Data inputs (P_n) into the flip-
flops This preset feature makes the circuit usable as a pro-
grammable counter The circuit can also be used as a 4-bit
latch loading data from the Parallel Data inputs when PL is
LOW and storing the data when PL is HIGH For detail spec-
ifications and functional description please refer to the
’LS196 data sheet
Features
Y _{High counting rates Typically 70 MHz}
Y _{Asynchronous preset}
Y _{Asynchronous master reset}
Connection Diagram
Dual-In-Line Package
TL F 10180 – 1
Order Number DM74LS197M or DM74LS197N
See NS Package Number M14A or N14A
Pin Names
Description
CP0
CP1
MR
P0 – P3
PL
Q0
Q1 – Q3
d2 Section Clock Input
(Active Falling Edge)
d8 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Input
(Active LOW)
Parallel Data Inputs
Asynchronous Parallel Load Input
(Active LOW)
d2 Section Output
d8 Section Outputs
Q0 output is guaranteed to drive the full rated fan-out plus the CP1 input
Mode Select Table
Inputs
MR
PL
CP
Response
L
X
X
Qn Forced LOW
H
L
X
PnxQn
H
H
K
Count Up
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
C1995 National Semiconductor Corporation TL F 10180
RRD-B30M105 Printed in U S A