DM74AS533 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – Octal D-Type Transparent Latch with TRI-STATE Outputs

December 1989
DM74AS533 Octal D-Type Transparent
Latch with TRI-STATE Outputs
General Description
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relative-
ly low-impedance loads The high-impedance state and in-
creased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components They are particularly attractive
for implementing buffer registers I O ports bidirectional
bus drivers and working registers
The eight inverting latches of the AS533 are transparent D-
type latches meaning that while the enable (G) is high the Q
outputs will follow the complement of the data (D) inputs
When the enable is taken low the output will be latched at
the complement of the level of the data that was set up
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state In the high-impedance
state the outputs neither load nor drive the bus lines signifi-
cantly
The output control does not affect the internal operation of
the latches That is the old data can be retained or new
data can be entered even while the outputs are off
Features
Y _{Switching specifications at 50 pF}
Y _{Switching specifications guaranteed over full tempera-}
ture and V_CC range
Y _{Advanced oxide-isolated ion-implanted Schottky TTL}
process
Y _{TRI-STATE buffer-type outputs drive bus lines directly}
Connection Diagram
Dual-In-Line Package
Order Number DM74AS533WM or DM74AS533N
See NS Package Number M20B or N20A
TL F 6311 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 6311
RRD-B30M105 Printed in U S A